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MC74VHC257DG

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 6
1 Publication Order Number:
MC74VHC257/D
MC74VHC257
Quad 2-Channel Multiplexer
with 3-State Outputs
The MC74VHC257 is an advanced high speed CMOS quad
2−channel multiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
It consists of four 2−input digital multiplexers with common select
(S) and enable (OE
) inputs. When (OE) is held High, selection of data
is inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
• High Speed: t
PD
= 4.1 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4.0 mA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: FETs = 100; Equivalent Gates = 25
• These Devices are Pb−Free and are RoHS Compliant
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
S
Y0
B0
A0
Y1
B1
A1
GND
Y3
B3
A3
OE
V
CC
B2
A2
Y2
Figure 1. Pin Assignment
http://onsemi.com
Device Package Shipping
ORDERING INFORMATION
MC74VHC257DG SO−16 48 Units/Rail
MC74VHC257DR2G SO−16
2500 Units/Ree
l
SO−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
MARKING DIAGRAMS
1
8
9
16
1
8
16 9
VHC257G
AWLYWW
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
VHC
257
ALYWG
G
MC74VHC257DTG TSSOP−16 96 Units/Rail
MC74VHC257DTR2G TSSOP−16 2500 Units/Ree
l
MC74VHC257
http://onsemi.com
2
Figure 2. Expanded Logic Diagram
OE S Y0 − Y3
A0 − A3, B0 − B3 = the levels
of the respective Data−Word
Inputs.
H
L
L
X
L
H
Z
A0−A3
B0−B3
Inputs
Outputs
3
OE
S
A0
B0
A1
B1
A2
B2
2
5
6
11
10
14
13
12
9
7
4
Y0
MUX
Y1
Y2
Y3
EN
1
15
A3
B3
G1
1
1
Figure 3. IEC Logic Symbol
FUNCTION TABLE
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
OE I
0a
I
1a
I
0b
I
1b
I
0c
I
1c
I
0d
I
1d
S
Z
a
Z
b
Z
c
Z
d
MC74VHC257
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
Positive DC Supply Voltage −0.5 to +7.0 V
V
IN
Digital Input Voltage −0.5 to +7.0 V
V
OUT
DC Output Voltage −0.5 to V
CC
+0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current $20 mA
I
OUT
DC Output Current, per Pin $25 mA
I
CC
DC Supply Current, V
CC
and GND Pins $75 mA
P
D
Power Dissipation in Still Air SOIC Package
TSSOP
200
180
mW
T
STG
Storage Temperature Range −65 to +150 °C
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
>2000
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125°C (Note 4) $300 mA
q
JA
Thermal Resistance, Junction−to−Ambient SOIC Package
TSSOP
143
164
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1 Tested to EIA/JESD22−A114−A
2 Tested to EIA/JESD22−A115−A
3 Tested to JESD22−C101−A
4 Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
IN
DC Input Voltage 0 5.5 V
V
OUT
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature Range, all Package Types −55 125 °C
t
r
, t
f
Input Rise or Fall Time V
CC
= 3.3 V + 0.3 V
V
CC
= 5.0 V + 0.5 V
0 100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
TIME, YEARS
NORMALIZED FAILURE RATE
T
J
= 80
C°
T
J
= 90
C°
T
J
= 100 C°
T
J
= 110 C°
T
J
= 130 C°
T
J
= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 4. Failure Rate vs. Time Junction Temperature
P1-P3P4-P6P7-P7

MC74VHC257DG

Mfr. #:
Buy MC74VHC257DG
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 2-5.5V Quad 3-State 2-Channel
Lifecycle:
New from this manufacturer.
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