7
FN3084.5
Differential Reference
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor large enough in comparison
to the stray capacitance, this error can be held to less than 0.5
count worst case. (See Component Value Selection.)
Analog COMMON
This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.8V
more negative than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6.8V.
However, analog COMMON has some of the attributes of a
reference voltage. When the total supply voltage is large
enough to cause the zener to regulate (<6.8V), the
COMMON voltage will have a low voltage coefficient
(0.001%/V), low output impedance (15), and a
temperature coefficient typically less than 80ppm/
o
C.
The limitations of the on-chip reference should also be
recognized, however. The reference Temperature Coefficient
(TC), can cause some degradation in performance.
Temperature changes of 2
o
C to 8
o
C, typical for instruments,
can give a scale factor error of a count or more. Also the
common voltage will have a poor voltage coefficient when the
total supply voltage is less than that which will cause the zener
to regulate (<7V). These problems are eliminated if an
external reference is used, as shown in Figure 5.
Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.
Within the lC, analog COMMON is tied to an N channel FET
that can sink approximately 3mA of current to hold the volt-
age 2.8V below the positive supply (when a load is trying to
pull the common line positive). However, there is only 1µA of
source current, so COMMON may easily be tied to a more
negative voltage thus overriding the internal reference.
FIGURE 5A.
FIGURE 5B.
FIGURE 5.
ICL7126
V+
REF LO
REF HI
V+
V-
6.8V
ZENER
I
Z
ICL7126
V+
REF HI
REF LO
COMMON
V+
ICL8069
1.2V
REFERENCE
27k
200k
ICL7126
8
FN3084.5
TEST
The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 500 resistor.
Thus it can be used as the negative supply for externally
generated segment drivers such as decimal points or any
other presentation the user may want to include on the LCD
display. Figures 6 and 7 show such an application. No more
than a 1mA load should be applied.
The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 10mA
under these conditions.
CAUTION: In the lamp test mode, the segments have a constant DC volt-
age (no square-wave) and may burn the LCD display if left in this mode for
several minutes.
Digital Section
Figure 8 shows the digital section for the ICL7126. An internal
digital ground is generated from a 6V Zener diode and a large
P-Channel source follower. This supply is made stiff to absorb
the relative large capacitive currents when the back plane (BP)
voltage is switched. The BP frequency is the clock frequency
divided by 800. For three readings/second this is a 60Hz
square wave with a nominal amplitude of 5V. The segments are
driven at the same frequency and amplitude and are in phase
with BP when OFF, but out of phase when ON. In all cases
negligible DC voltage exists across the segments. The polarity
indication is “ON” for negative analog inputs. If IN LO and IN HI
are reversed, this indication can be reversed also, if desired.
System Timing
Figure 9 shows the clocking arrangement used in the
ICL7126. Two basic clocking arrangements can be used:
Figure 9A, an external oscillator connected to pin 40.
Figure 9B, an R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000 counts),
reference de-integrate (0 to 2000 counts) and auto-zero (1000
to 3000 counts). For signals less than full-scale, auto-zero gets
the unused portion of reference de-integrate. This makes a
complete measure cycle of 4,000 counts (16,000 clock pulses)
independent of input voltage. For three readings/second, an
oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 60kHz, 48kHz, 40kHz, 33
1
/
3
kHz, etc. should
be selected. For 50Hz rejection, oscillator frequencies of
66
2
/
3
kHz, 50kHz, 40kHz, etc. would be suitable. Note that
40kHz (2.5 readings/sec.) will reject both 50Hz and 60Hz
(also 400Hz and 440Hz).
ICL7126
V+
BP
TEST
21
37
TO LCD
BACKPLANE
TO LCD
DECIMAL
POINT
1M
ICL7126
V+
BP
TEST
DECIMAL
POINT
SELECT
CD4030
GND
V+
TO LCD
DECIMAL
POINTS
V+ = DP ON
GND = DP OFF
FIGURE 7. EXCLUSIVE ‘OR’ GATE FOR
DECIMAL POINT DRIVE
ICL7126
FIGURE 6. SIMPLE INVERTER FOR FIXED
DECIMAL POINT
9
FN3084.5
7
SEGMENT
DECODE
SEGMENT
OUTPUT
0.5mA
2mA
INTERNAL DIGITAL GROUND
TYPICAL SEGMENT OUTPUT
V+
LCD PHASE DRIVER
LATCH
7
SEGMENT
DECODE
÷200
LOGIC CONTROL
INTERNAL
V
TH
= 1V
a
b
c
d
e
f
g
a
b
7
SEGMENT
DECODE
1000’s 100’s 10’s 1’s
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL
GROUND
÷4
CLOCK
40 39 38
OSC 1
OSC 2
OSC 3
BACKPLANE
21
V+
TEST
V-
500
37
26
6.2V
COUNTER COUNTER COUNTER COUNTER
35
1
HLDR
THREE INVERTERS.
ONE INVERTER SHOWN FOR CLARITY.
FIGURE 8. DIGITAL SECTION
CLOCK
INTERNAL TO PART
40 39
38
÷4
TEST ICL7126
CLOCK
INTERNAL TO PART
40 39
38
÷4
R
C
FIGURE 9. CLOCK CIRCUITS
FIGURE 9A. EXTERNAL SIGNAL
FIGURE 9B. RC OSCILLATOR
ICL7126

ICL7126CPLZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LCD Drivers ADC 3 5 DIG LCD DRVR LWPWR COM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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