Philips Semiconductors Product data
PTN3310/PTN3311High-speed serial logic translators
2004 Feb 24
5
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min Typ Max Unit
General
f
MAX
Maximum throughput data rate 655 800 – Mbps
Clock output skew, part-to-part – 100 – ps
SKEW
Clock output pulse skew – 50 – ps
Propagation delay input (differential) to output – 1 3 ns
PLH
PHL
Propagation delay input (single-ended) to output – 1 3 ns
PECL outputs (PTN3310)
t
r
/t
f
Output rise and fall times at 20% and 80%
intersects
– 200 300 ps
LVDS outputs (PTN3311); R
L
= 100 Ω; C
L
= 5 pF
t
TLH
Transition time LOW to HIGH R
L
= 100 Ω; C
L
= 5 pF – 500 650 ps
t
THL
Transition time HIGH to LOW R
L
= 100 Ω; C
L
= 5 pF – 500 650 ps
V
OSS
Peak-to-peak switching offset voltage
Measured between two
matched 49.9 Ω load resistors;
5 pF load capacitance
– – 150 mV
LVDS REFERENCE MEASUREMENT CONFIGURATION
ST00041
PTN331x
C
LVDS
R
load
R
load
Vos
Voutp
C
probe
C
probe
Voutn
V
OD
= V
OUTP
– V
OUTN
R
load
= 50 Ω
C
LVDS
= 5 pF
1
2
3
4
5
6
7
8
Figure 3.
The above diagram shows the test set-up used when evaluating
LVDS outputs. According to the TIA-EIA-644 Standard, the
maximum lumped capacitance test load should be 5 pF. However,
by using probes or cables to observe the signal, additional
capacitance is added, which has an effect on the rise and fall times.
C
probe
represents any capacitance caused by the use of probes or
cables. Assuming balanced loading and balanced output drivers, the
total effective capacitance seen by the part is:
C
Eff
= C
LVDS
+
1
/
2
C
probe
To correctly account for the effects of C
probe
, the following formula
should be used:
Dt +
5pF
C
Eff
Dt
measured,
Where ∆t is the 20%–80% rise/fall time.
To avoid the use of additional calculation of the measured results, a
different approach could be taken; however, the value of C
probe
has
to be known in advance. In that case, the value of C
LVDS
can be
chosen such that the sum of the capacitances equals 5 pF, i.e.:
C
LVDS
+
1
/
2
C
probe
= 5 pF
