OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC74VHCT126ADR2

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2016
October, 2016 − Rev. 11
1 Publication Order Number:
MC74VHCT126A/D
MC74VHCT126A
Quad Bus Buffer
with 3−State Control Inputs
The MC74VHCT126A is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves
noninverting high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHCT126A requires the 3−state control input (OE) to be
set Low to place the output into high impedance.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT126A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4.0 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
See detailed ordering and shipping information in the packag
e
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
A
H
L
X
FUNCTION TABLE
Inputs Outputs
OE
H
H
L
Y
H
L
Z
VHCT126A
MARKING
DIAGRAMS
SOIC−14
D SUFFIX
CASE 751A
1
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
VHCT126AG
AWLYWW
1
14
See Applications Note #AND8004/D for
date code and traceability information.
TSSOP−14
DT SUFFIX
CASE 948G
1
VHCT
126A
ALYWG
G
1
14
(Note: Microdot may be in either location)
MC74VHCT126A
www.onsemi.com
2
Figure 1. LOGIC DIAGRAM
Active−High Output Enables
Y1
Y2
Y4
3
6
8
11
13
12
10
9
4
5
1
2
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
11
12
13
14
8
9
105
4
3
2
1
7
6
OE3
Y4
A4
OE4
V
CC
Y3
A3
OE2
Y1
A1
OE1
GND
Y2
A2
Figure 2. PIN ASSIGNMENT
MAXIMUM RATINGS
Rating Symbol Value Unit
DC Supply Voltage V
CC
– 0.5 to + 7.0 V
DC Input Voltage V
in
– 0.5 to + 7.0 V
DC Output Voltage Output in 3−State
High or Low State
V
out
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
V
Input Diode Current I
IK
− 20 mA
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
) I
OK
± 20 mA
DC Output Current, per Pin I
out
± 25 mA
DC Supply Current, V
CC
and GND Pins I
CC
± 75 mA
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
P
D
500
450
mW
Storage Temperature T
stg
– 65 to + 150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
DC Supply Voltage V
CC
4.5 5.5 V
DC Input Voltage V
in
0 5.5 V
DC Output Voltage Output in 3−State
High or Low State
V
out
0
0
5.5
V
CC
V
Operating Temperature T
A
− 40 + 85
_C
Input Rise and Fall Time V
CC
= 5.0 V ±0.5 V t
r
, t
f
0 20 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHCT126A
www.onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Symbo
l
V
CC
(V)
T
A
= 25°C T
A
≤ 85°C T
A
≤ 125°C
Uni
t
Min Typ Max Min Max Min Max
Minimum High−Level Input
Voltage
V
IH
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
Maximum Low−Level Input
Voltage
V
IL
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
Minimum High−Level Output
Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= − 50 mA
V
OH
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= − 4.0 mA
I
OH
= − 8.0 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
Maximum Low−Level Output
Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
V
OL
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4.0 mA
I
OL
= 8.0 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
Maximum Input Leakage Current V
IN
= 5.5 V or GND I
IN
0 to 5.5 ± 0.1 ± 1.0 ± 1.0
mA
Maximum Quiescent Supply
Current
V
IN
= V
CC
or GND I
CC
5.5 2.0 20 40
mA
Quiescent Supply Current Input: V
IN
= 3.4 V I
CCT
5.5 1.35 1.50 1.65 mA
Maximum 3−State Leakage
Current
V
IN
= V
IH
or V
I
V
OUT
= V
CC
or GND
I
OZ
5.5 ±0.2
5
±2.5 ±2.5
mA
Output Leakage Current V
OUT
= 5.5 V I
OPD
0.0 0.5 5.0 10
mA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns)
Parameter Test Conditions Symbo
l
T
A
= 25°C T
A
= ≤ 85°C T
A
≤ 125°C
Uni
t
Min Typ Max Min Max Min Max
Maximum Propagation Delay,
A to Y
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
t
PLH
,
t
PHL
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
12.0
16.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15 pF
C
L
= 50 pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
8.5
10.5
Maximum Output Enable
TIme,OE
to Y
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
R
L
= 1.0 kW C
L
= 50 pF
t
PZL
,
t
PZH
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
11.5
15.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15 pF
R
L
= 1.0 kW C
L
= 50 pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
7.5
9.5
Maximum Output
Disable Time,OE
to Y
V
CC
= 3.3 ± 0.3 V C
L
= 50 pF
R
L
= 1.0 kW
t
PLZ
,
t
PHZ
9.5 13.2 1.0 15.0 18.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 50 pF
R
L
= 1.0 kW
6.1 8.8 1.0 10.0 12.0
Output−to−Output Skew
V
CC
= 3.3 ± 0.3 V C
L
= 50 pF
(Note 1)
t
OSLH
,
t
OSHL
1.5 1.5 2.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 50 pF
(Note 1)
1.0 1.0 1.5
Maximum Input Capacitance C
in
4 10 10 10 pF
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
C
out
6 pF
Power Dissipation Capacitance (Note 2) C
PD
Typical @ 25°C, V
CC
= 5.0V
pF
15
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
− t
PLHn
|, t
OSHL
= |t
PHLm
− t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per buffer). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
P1-P3P4-P6

MC74VHCT126ADR2

Mfr. #:
Buy MC74VHCT126ADR2
Manufacturer:
ON Semiconductor
Description:
IC BUF NON-INVERT 5.5V 14SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet