7
LTC1746
1746f
2nd and 3rd Harmonic vs Input
Frequency, 3.2V Range, –1dB
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–70
–50
–30
80
1746 G17
–90
–110
–130
10 20 30
40 50
60 70 90
100
2ND HARMONIC
3RD HARMONIC
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–70
–50
–30
100
1746 G18
–90
–110
–130
50 150 200
2ND HARMONIC
3ND HARMONIC
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–80
–70
–60
80
1746 G19
–90
–100
–110
10 20 30
40 50
60 70 90
100
2nd and 3rd Harmonic vs Input
Frequency, 2V Range, –1dB
Worst Harmonic 4th or Higher vs
Input Frequency, 3.2V Range, –1dB
Worst Harmonic 4th or Higher vs
Input Frequency, 2V Range, –1dB
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–80
–70
–60
100
1746 G20
–90
–100
–110
50 150 200
SFDR vs Input Amplitude,
2V Range, 5MHz Input Frequency
INPUT AMPLITUDE (dBFS)
–60
SFDR (dBc AND dBFS)
80
90
SFDR dBFS
SFDR dBc
1746 G21
70
60
–40
–20
0
110
100
Power vs Sample Rate,
Input Frequency = 5MHz
SAMPLE RATE (Msps)
0
300
POWER (mW)
340
380
420
10
20
30 40
1746 G22
50
460
500
320
360
400
440
480
60
3.2V RANGE
2V RANGE
8
LTC1746
1746f
SENSE (Pin 1): Reference Sense Pin. Ground selects
±1V. V
DD
selects ±1.6V. Greater than 1V and less than
1.6V applied to the SENSE pin selects an input range of
±V
SENSE
, ±1.6V is the largest valid input range.
V
CM
(Pin 2): 2.35V Output and Input Common Mode Bias.
Bypass to ground with 4.7µF ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC
Power Ground.
A
IN
+
(Pin 4): Positive Differential Analog Input.
A
IN
(Pin 5): Negative Differential Analog Input.
V
DD
(Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to GND
with 1µF ceramic chip capacitor.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10
with 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF
ceramic capacitor and to ground with 1µF ceramic
capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15
with 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF
ceramic capacitor and to ground with 1µF ceramic
capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 11.
PI FU CTIO S
UUU
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on
the positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended encode signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs. D0 is the LSB.
OV
DD
(Pins 32, 43): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1µF ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs. D13 is the
MSB.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
9
LTC1746
1746f
14-BIT
PIPELINED ADC
14
S/H
AMP
±1V
DIFFERENTIAL
ANALOG INPUT
A
IN
+
A
IN
SENSE
V
CM
4.7µF
DIFF AMP
REFLA REFHB
GND
1746 BD
ENC
4.7µF
1µF1µF
0.1µF 0.1µF
REFHAREFLB
BUFFER
RANGE
SELECT
2.35V
REF
OUTPUT
LATCHES
CONTROL LOGIC
OV
DD
V
DD
OGND
0.5V TO 5V
5V
0.1µF
1µF 1µF 1µF
D13
D0
CLKOUT
OF
ENC
DIFFERENTIAL
ENCODE INPUT
OEMSBINV
0.1µF
t
4
1746 TD
t
3
t
6
t
5
t
5
N
t
1
t
2
DATA (N – 5)
D11 TO D0
ANALOG
INPUT
ENCODE
DATA
CLKOUT
DATA (N – 4)
D11 TO D0
DATA (N – 3)
D11 TO D0
t
7
t
8
DATA N
D11 TO D0, OF AND CLKOUT
OE
DATA
TI I G DIAGRA
UWW
FU CTIO AL BLOCK DIAGRA
UU
W

LTC1746IFW#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC L Pwr,14-B, 25Msps ADC
Lifecycle:
New from this manufacturer.
Delivery:
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