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9DB423BFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
ICS9DB423B
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI
IDT®
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI 7
ICS9DB423B REV E 091812
Electrical Characteristics–DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33
Ω
, R
P
=49.9
Ω
, R
REF
=475
Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Impedance
Zo
1
3000
Ω
1
Voltage High VHigh 660 850 1,2
Voltage Low VLow -150 150 1,2
Max Voltage Vovs 1150 1
Min Voltage Vuds -300 1
Crossing Voltage (abs) Vcross(abs) 250 550 mV 1
Crossing Voltage (var) d-Vcross Variation of crossing over all edges 140 mV 1
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time t
f
V
OH
= 0.525V V
OL
= 0.175V 175 700 ps 1
Rise Time Variation d-t
r
125 ps 1
Fall Time Variation d-t
f
125 ps 1
Duty Cycle d
t3
Measurement from differential wavefrom 45 55 % 1
t
p
dBYP
Bypass Mode, V
T
= 50% 2500 4500 ps 1
t
p
dPLL
PLL Mode V
T
= 50% -250 250 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 50 ps 1
PLL mode 50 ps 1,3
Additive Jitter in Bypass Mode 50 ps 1,3
PCIe Gen1 phase jitter
(Additive in Bypass Mode)
710
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter
(Additive in Bypass Mode)
00.1
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
0.7 0.9
ps
(rms)
1,4,5
QPI phase jitter
(Additive in Bypass Mode)
0.16
ps
(rms)
1,5,6
PCIe Gen 1 phase jitter 37 86
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter 1.5 3
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
2.7/
2.2
3.1
ps
(rms)
1,4,5,7
QPI phase jitter 0.28 0.5
ps
(rms)
1,5,6
1
Guaranteed by design and characterization, not 100% tested in production.
2
I
RE
F
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
3 Measured from differential waveform
4
See http://www.pcisig.com for complete specs
5
Device driven by 932S421C or equivalent.
6
6.4Gb 12UI
7
First number is High Bandwidth Mode, second number is Low Bandwidth Mode
t
jphasePLL
Skew, Input to Output
Statistical measurement on single ended
signal using oscilloscope math function.
mV
Measurement on single ended signal
using absolute value.
mV
Jitter, Cycle to cycle t
jcyc-cyc
t
jphaseBYP
Jitter, Phase
ICS9DB423B
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI
IDT®
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI 8
ICS9DB423B REV E 091812
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Clock Periods–Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm
+
pp
m error
+SSC Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
DIF 100
9.949 9.999 10.024 10.025 10.026 10.051 10.101
ns 1,2,3
DIF 133
7.449 7.499 7.518 7.519 7.520 7.538 7.588
ns 1,2,4
DIF 166
5.949 5.999 6.014 6.015 6.016 6.031 6.081
ns 1,2,5
DIF 200
4.950 5.000 5.012 5.013 5.013 5.026 5.076
ns 1,2,5
DIF 266
3.700 3.750 3.759 3.759 3.760 3.769 3.819
ns 1,2,5
DIF 333
2.950 3.000 3.007 3.008 3.008 3.015 3.065
ns 1,2,5
DIF 400
2.450 2.500 2.506 2.506 2.507 2.513 2.563
ns 1,2,5
Units
Signal Name
Measurement
Window
Symbol
Notes
Definition
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm
+
pp
m error
+SSC Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
DIF 100
9.949 9.999 10.000 10.001 10.051 ns 1,2,3
DIF 133
7.449 7.499 7.500 7.501 7.551 ns 1,2,4
DIF 166
5.949 5.999 6.000 6.001 6.051 ns 1,2,5
DIF 200
4.950 5.000 5.000 5.001 5.051 ns 1,2,5
DIF 266
3.700 3.750 3.750 3.750 3.800 ns 1,2,5
DIF 333
2.950 3.000 3.000 3.000 3.050 ns 1,2,5
DIF 400
2.450 2.500 2.500 2.500 2.550 ns 1,2,5
1
Guaranteed by design and characterization, not 100% tested in production.
3
Driven by SRC output of main clock, PCIe PLL Mode or Bypass mode
4
Driven by CPU output of main clock, QPI PLL Mode or Bypass mode
5
Driven by CPU output of CK410B+/CK420BQ/CK505 main clock,
Bypass mode only
Definition
Signal Name
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+ accuracy
requirements. The 9DB423/823 itself does not contribute to ppm error.
Notes
Measurement
Window
Units
Symbol
ICS9DB423B
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI
IDT®
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI 9
ICS9DB423B REV E 091812
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
DIF Reference Clock
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

9DB423BFLFT

Mfr. #:
Buy 9DB423BFLFT
Manufacturer:
IDT
Description:
Clock Buffer 4 OUTPUT PCIE GEN2 BUFFER w/QPI
Lifecycle:
New from this manufacturer.
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