DS1231-35

DS1231/S
DS1231/S
Power Monitor Chip
022698 1/9
FEATURES
Warns processor of an impending power failure
Provides time for an orderly shutdown
Prevents processor from destroying nonvolatile
memory during power transients
Automatically restarts processor after power is
restored
Suitable for linear or switching power supplies
Adjusts to hold time of the power supply
Supplies necessary signals for processor interface
Accurate 5% or 10% V
CC
monitoring
Replaces power-up reset circuitry
No external capacitors required
Optional 16-pin SOIC surface mount package
PIN ASSIGNMENT
MODE
NC
GND
RST
NC
VCC
NC
NMI
NC
RST
NC
NC
TOL
NC
IN
NC
DS1231S 16–Pin SOIC
(300 MIL)
See Mech. Drawings
Section
VCC
NMI
RST
RST
IN
MODE
TOL
GND
DS1231 8–Pin DIP
(300 MIL)
See Mech. Drawings
Section
1
2
3
4
5
6
7
8
1
11
12
13
14
2
3
4
5
6
7
8
9
10
15
16
PIN DESCRIPTION
IN Input
MODE Selects input pin characteristics
TOL Selects 5% or 10% V
CC
detect
GND Ground
RST Reset (Active High)
RST
Reset (Active Low, open drain)
NMI
Non–Maskable Interrupt
V
CC
+5V Supply
NC No Connections
DESCRIPTION
The DS1231 Power Monitor Chip uses a precise tem-
perature-compensated reference circuit which provides
an orderly shutdown and an automatic restart of a pro-
cessor-based system. A signal warning of an impending
power failure is generated well before regulated DC
voltages go out of specification by monitoring high volt-
age inputs to the power supply regulators. If line isola-
tion is required a UL-approved opto-isolator can be di-
rectly interfaced to the DS1231. The time for processor
shutdown is directly proportional to the available
hold-up time of the power supply. Just before the
hold-up time is exhausted, the Power Monitor uncondi-
tionally halts the processor to prevent spurious cycles
by enabling Reset as V
CC
falls below a selectable 5 or
10 percent threshold. When power returns, the proces-
sor is held inactive until well after power conditions have
stabilized, safeguarding any nonvolatile memory in the
system from inadvertent data changes.
DS1231/S
022698 2/9
OPERATION
The DS1231 Power Monitor detects out-of-tolerance
power supply conditions and warns a processor-based
system of impending power failure. The main elements
of the DS1231 are illustrated in Figure 1. As shown, the
DS1231 actually has two comparators, one for monitor-
ing the input (Pin 1) and one for monitoring V
CC
(Pin 8).
The V
CC
comparator outputs the signals RST (Pin 5)
and RST (Pin 6) when V
CC
falls below a preset trip level
as defined by TOL (Pin 3).
When TOL is connected to ground, the RST and RST
signals will become active as V
CC
goes below 4.75
volts. When TOL is connected to V
CC
, the RST and RST
signals become active as V
CC
goes below 4.5 volts. The
RST and RST signals are excellent control signals for a
microprocessor, as processing is stopped at the last
possible moments of valid V
CC
. On power-up, RST and
RST are kept active for a minimum of 150 ms to allow the
power supply to stabilize (see Figure 2).
The comparator monitoring the input pin produces the
NMI
signal (Pin 7) when the input threshold voltage
(V
TP
) falls to a level as determined by Mode (Pin 2).
When the Mode pin is connected to V
CC
, detection oc-
curs at V
TP
-. In this mode Pin 1 is an extremely high im-
pedance input allowing for a simple resistor voltage di-
vider network to interface with high voltage signals.
When the Mode pin is connected to ground, detection
occurs at V
TP
+. In this mode Pin 1 sources 30 µA of cur-
rent allowing for connection to switched inputs, such as
a UL-approved opto-isolator. The flexibility of the input
pin allows for detection of power loss at the earliest point
in a power supply system, maximizing the amount of
time allotted between NMI
and RST. On power-up, NMI
is released as soon as the input threshold voltage (V
TP
)
is achieved and V
CC
is within nominal limits. In both
modes of operation the input pin has hysteresis for
noise immunity (Figure 3).
APPLICATION – MODE PIN
CONNECTED TO V
CC
When the Mode pin is connected to V
CC
, pin 1 is a high
impedance input. The voltage sense point and the level
of voltage at the sense point are dependent upon the
application (Figure 4). The sense point may be devel-
oped from the AC power line by rectifying and filtering
the AC. Alternatively, a DC voltage level may be se-
lected which is closer to the AC power input than the
regulated +5-volt supply, so that ample time is provided
for warning before regulation is lost.
Proper operation of the DS1231 requires a maximum
voltage of 5 volts at the input (Pin 1), which must be
derived from the maximum voltage at the sense point.
This is accomplished with a simple voltage divider net-
work of R1 and R2. Since the IN trip point V
TP
- is 2.3
volts (using the -20 device), and the maximum allowable
voltage on pin 1 is 5 volts, the dynamic range of voltage
at the sense point is set by the ratio of 2.3/5.0=.46 min.
This ratio determines the maximum deviation between
the maximum voltage at the sense point and the actual
voltage which will generate NMI
.
Having established the desired ratio, and confirming
that the ratio is greater than .46 and less than 1, the
proper values for R1 and R2 can be determined by the
equation as shown in Figure 4. A simple approach to
solving this equation is to select a value for R2 which is
high enough impedance to keep power consumption
low, and solve for R1. Figure 5 illustrates how the
DS1231 can be interfaced to the AC power line when
the mode pin is connected to V
CC
.
DS1231/S
022698 3/9
POWER MONITOR BLOCK DIAGRAM Figure 1
NMI
MODE
SELECTION
30A
IN
1
TOLERANCE
BIAS
DIGITAL
SAMPLER
DIGITAL
DELAY
4
8
3
T.C. REFERENCE
GND
TOL
V
CC
6
5
RST
MODE
NMI
2
7
RST
V
CC
POWER-UP RESET Figure 2
DS1231
V
CC
NMI
RST
RST
IN
MODE
TOL
GND
MICROPROCESSOR
NC
+5V
RST
(-5% V
CC
THRESHOLD)
8051
µP

DS1231-35

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits Power Monitor
Lifecycle:
New from this manufacturer.
Delivery:
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