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74HC191D,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 12 of 22
NXP Semiconductors
74HC191
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 11. The clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation delays
DDD
9
0
W
3+/
W
3/+
9
,
*1'
&3
&(LQSXW
9
2+
9
2/
9
0
5&RXWSXW
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 12. The input (Dn) to output (Qn) propagation delays
DDD
9
0
W
3+/
W
3/+
9
,
*1'
'QLQSXW
9
2+
9
2/
9
0
4QRXWSXW
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 13. The parallel load input (PL) to output (Qn) propagation delays
DDD
9
0
9
0
9
O
9
O
*1'
'QLQSXW
3
/LQSXW
4QRXWSXW
*1'
9
2+
9
2/
W
3/+
W
3+/
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 13 of 22
NXP Semiconductors
74HC191
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 14. The up/down count input (U/D) to terminal count and ripple clock output (TC, RC) propagation delays
DDD
9
0
9
,
*1'
9
2+
9
2+
9
2/
9
2/
9
0
9
0
W
3/+
W
3+/
W
3/+
W
3+/
8'LQSXW
7&RXWSXW
5&RXWSXW
Measurement points are given in Table 9.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 15. The parallel load input (PL) to clock (CP) recovery times, parallel load pulse width and output (Qn)
transition times
DDD
9
2+
9
2/
9
0
9
,
9
,
*1'
*1'
W
7/+
W
7+/
9
0
9
0
W
:
W
UHF
W
3+/
 

4QRXWSXW
3
/LQSXW
&3LQSXW
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 14 of 22
NXP Semiconductors
74HC191
Presettable synchronous 4-bit binary up/down counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 9
.
Fig 16. The parallel load input (PL) to data input (Dn) set-up and hold times
DDD
9
0
*1'
'QLQSXW
*1'
W
K
3/LQSXW
9
0
W
VX
W
VX
W
K
9
O
9
O
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 9
.
Fig 17. The count enable and up/down count inputs (CE, U/D) to clock input (CP) set-up and hold times
DDD
*1'
*1'
9
O
9
0
&3LQSXW
*1'
9
0
9
0
&(8'LQSXW
&(8'LQSXW
9
O
9
O
W
VX
W
K
W
K
W
VX
Table 9. Measurement points
Input Output
V
M
V
I
V
M
0.5 V
CC
GND to V
CC
0.5 V
CC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

74HC191D,652

Mfr. #:
Buy 74HC191D,652
Manufacturer:
Nexperia
Description:
Counter ICs SYNC BIN U/D COUNTER
Lifecycle:
New from this manufacturer.
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