LTC4350
13
4350fb
applicaTions inForMaTion
The resistors R
OUT
and R
SET
set the adjustment range.
The voltage on R
SET
is translated to a voltage on R
OUT
by the ratio of R
OUT
/R
SET
. Therefore, the adjustment on
the output voltage will track the voltage at the R
SET
pin
which is also the voltage on the COMP2 pin minus a diode
voltage. The expression is V
ADJ
= (V
RSET
) • R
OUT
/R
SET
=
(V
COMP2
– V
DIODE
) • R
OUT
/R
SET
. The maximum voltage at
V
RSET
is limited to 1V. The maximum adjustment on the
output is expressed as V
ADJMAX
= R
OUT
/R
SET
. A normal
value for R
SET
is in the 50Ω to 100Ω range.
If we set R
SET
to be 100Ω, then an R
OUT
of 100Ω allows
the output voltage a full 1V adjustment. For the 0.3V range
in this example, the R
OUT
is 30Ω. In some power modules,
there already exists a resistor between the SENSE
+
line
and the power output. In this case, the value of R
OUT
is the
parallel combination of two resistors, one in the module
and one placed between the SENSE
+
and output terminals
of the module.
The value of the gain setting resistor, R
GAIN,
depends on
the maximum voltage drop across the sense resistor and
the supply voltage V
CC
for the chip. The highest possible
voltage at the GAIN pin is 1.5V from the V
CC
voltage.
The maximum voltage on the GAIN pin is expressed as:
V
GAINMAX
= R
SENSE
• I
MAX
• R
GAIN
/1k = V
CC
– 1.5V. The
expression for R
GAIN
: R
GAIN
= (V
CC
– 1.5V) • 1k/(R
SENSE
•
I
MAX
). In this example, V
CC
is 5V, I
MAX
is 20A and R
SENSE
is 0.002Ω. Therefore, R
GAIN
is 87.5k but using 1% values
results in 86.6k.
The FB pin divider provides a 1.220V output for a 5V
input. The precision of the FB pin divider resistors will
impact the accuracy of the final output voltage. The UV
resistive divider in this example, turns on the gate when
V
CC
increases above 4V. This corresponds to the UV pin at
1.220V. The capacitor C
UV
prevents false activation during
load steps. The OV set point needs to occur above the
adjustment max for V
CC
. The power supply output (which
also is V
CC
), can start as high as 5V and adjust upwards
to 5.3V. The OV set point in this example is 5.5V on V
CC
when the OV pin is at 1.220V.
The timer capacitor C
T
is set to be 0.1µF for a 61ms
timer cycle. The expression is t = C
T
• 1.22V/2µA. The
gate capacitor C
G
is set to be 0.1µF which sets a slope
of 10µA/C
G
or 1V every 10ms. In this case, the GATE pin
must charge up to 9V before the output can ramp to 5V
which happens in 90ms. In this case, the output adjust
soft-start turns on when the gate ramps above 9V. The
soft-start circuitry releases the COMP2 pin allowing the
load sharing loop to function. A 100Ω resistor R
G
prevents
high frequency oscillations from the power FETs at their
turn-on threshold. A 0.1µF bypass capacitor is required on
the V
CC
pin. If the V
CC
pin is tied to the same power sup-
ply output that is being adjusted, then a 51Ω decoupling
resistor is needed to hold up the supply during a short to
ground on the supply output.
C
OMPENSATION
The compensation capacitor, C
P1
, is needed to set the
crossover frequency of the feedback error amplifier E/A1.
The crossover frequency of 200kHz is adequate for most
applications and requires C
P1
to be 1000pF (0.001µF).
The design of the other compensation capacitor will require
some knowledge about the power supply’s bandwidth. The
bandwidth can be measured easily. First, use a storage
oscilloscope to monitor the power supply output voltage.
Then place a 1A resistive fixed load and switch in a second
resistive load that increases the total load current close
to rated maximum. Tapping the second resistor (with
the correct power rating) to the power supply output
creates this load step. Trigger the scope on the falling
edge of the output voltage as it drops more than 100mV
(for example from 5V to 4.8V). The recovery time, t
R
,
from the step needs to be measured. t
R
is defined as
the 10% to 90% time measurement (see Figure 6). The
V
OUT
(t)
4350 F06
t
t
r
0.1∆V
∆V
0.1∆V
90%
10%
Figure 6. t
R
Measurement
