DATASHEET
9DBU0931 MARCH 9, 2017 1 ©2017 Integrated Device Technology, Inc.
9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer 9DBU0931
Description
The 9DBU0931 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
9 1–167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter < 5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is < 300fs rms for PCIe Gen 3
DIF additive phase jitter < 350fs rms for SGMII
Features/Benefits
LP-HCSL outputs; save 18 resistors compared to standard
HCSL outputs
47mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
6 × 6 mm 48-VFQFPN; minimal board space
Block Diagram
CONTROL
LOGIC
^CKPWRGD_PD#
SDATA_3.3
vOE(8:0)#
SCLK_3.3
vSADR
CLK_IN
9
CLK_IN#
DIF8
DIF4
DIF3
DIF1
DIF0
DIF2
DIF5
DIF7
DIF6
9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER 2 MARCH 9, 2017
9DBU0931 DATASHEET
Pin Configuration
SMBus Address Selection Table
Power Management Table
Power Connections
^CKPWRGD_PD#
VDDIO
vOE7#
DIF7#
DIF7
vOE6#
DIF6#
DIF6
GND
VDDIO
VDD1.5
vOE5#
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1 36 DIF5#
vOE8# 2 35 DIF5
DIF8 3 34 vOE4#
DIF8# 4 33 DIF4#
VDDR1.5 5 32 DIF4
CLK_IN 6 31 VDDIO
CLK_IN# 7 30 VDDO1.5
GNDR 8 29 GND
GNDDIG 9 28 vOE3#
SCLK_3.3 10 27 DIF3#
SDATA_3.311 26DIF3
VDDDIG1.512 25vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
VDDIO
vOE0#
DIF0
DIF0#
vOE1#
DIF1
DIF1#
VDD1.5
VDDIO
GND
DIF2
DIF2#
^v
v
^
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
prefix indicates internal 120KOhm pull down resisto
r
prefix indicates internal 120KOhm pull up resistor
prefix indicates internal 120KOhm pull up AND pull
down resistor (biased to VDD/2)
9DBU0931
epad is GND
SADR Address
0 1101011
M 1101100
1 1101101
x
State of SADR on first application of
CKPWRGD_PD#
+ Read/Write bit
x
x
True O/P Comp. O/P
0XXXLowLow
1 Running 0 X Low Low
1 Running 1 0 Running Running
1 Running 1 1 Low Low
DIFx
CKPWRGD_PD#
SMBus
OEx bit
CLK_IN OEx# Pin
VDD VDDIO GND
58
Input
receiver
analog
12 9 Di
g
ital power
20,30,31,38 13,21,31,39,47 22,29,40 DIF outputs
Note: EPAD on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
Description
Pin Number
MARCH 9, 2017 3 9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER
9DBU0931 DATASHEET
Pin Descriptions
3 DIF8 OUT Differential true clock output.
6 CLK_IN IN True input for differential reference clock.
8 GNDR GND Analog ground pin for the differential input (receiver)
10 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
12 VDDDIG1.5 PWR 1.5V digital power (dirty power)
15 DIF0 OUT Differential true clock output.
18 DIF1 OUT Differential true clock output.
20 VDD1.5 PWR Power supply, nominally 1.5V
22 GND GND Ground pin.
24 DIF2# OUT Differential complementary clock output.
down.
27 DIF3# OUT Differential complementary clock output.
down.
30 VDDO1.5 PWR Power supply for outputs, nominally 1.5V.
32 DIF4 OUT Differential true clock output.
35 DIF5 OUT Differential true clock output.
38 VDD1.5 PWR Power supply, nominally 1.5V

9DBU0931AKLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2 O/P 1.5V PCIE 56mW GEN1-2-3 Com Temp
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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