AQD-D4U16E24-SE Datasheet AQD-D4U16E24-SE | P7-P9

288 Pin DDR4 1.2V 2400 ECC UDIMM

16GB Based on 1Gx8

AQD-D4U16E24-SE

Advantech

Block Diagram

16GB, 2Gx72 Module(2 Rank x8)

This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either

expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes

in specifications at any time without prior notice.

288 Pin DDR4 1.2V 2400 ECC UDIMM

16GB Based on 1Gx8

AQD-D4U16E24-SE

Advantech

Operating Temperature Condition

Parameter Symbol Rating Unit Note

Operating Temperature TOPER 0 to 85C1,2

Note:

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51-2 standard.

2. At 0 - 85C, operation temperature range are the temperature which all DRAM specification will be

supported.

Absolute Maximum DC Ratings

Parameter Symbol Value Unit Note

Voltage on VDD relative to Vss VDD -0.3 ~ 1.5 V 1,3

Voltage on VDDQ pin relative to Vss VDDQ -0.3 ~ 1.5 V 1,3

Voltage on VPP pin relative to Vss VPP -0.3 ~ 3.0 V 4

Voltage on any pin relative to Vss VIN, VOUT -0.3 ~ 1.5 V 1,3

Storage temperature TSTG -55~+100C 1,2

Note:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times and VREFCA must be not greater than

0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV

4. VPP must be equal or greater than VDD/VDDQ at all times.

AC & DC Operating Conditions

Recommended DC operating conditions

Symbol Parameter

Rating

Unit NOTE

Min. Typ. Max.

VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3

VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 3

NOTE:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. DC bandwidth is limited to 20MHz.

AC & DC Logic Input Levels for Single-Ended Signals

Symbol Parameter

DDR4-1600/1866/2133/2400

Unit NOTE

Min. Max.

VIH.CA(DC75) DC input logic high VREFCA+ 0.075 VDD V

VIL.CA(DC75) DC input logic low VSS VREFCA-0.075 V

VIH.CA(AC100) AC input logic high VREF + 0.1 Note 2 V 1

VIL.CA(AC100) AC input logic low Note 2 VREF - 0.1 V 1

VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49*VDD 0.51*VDD V 2,3

NOTE :

1. See “Overshoot and Undershoot Specifications” on section.

2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for

reference : approx. ± 12mV)

3. For reference : approx. VDD/2 ± 12mV

288 Pin DDR4 1.2V 2400 ECC UDIMM

16GB Based on 1Gx8

AQD-D4U16E24-SE

Advantech

Timing Parameters & Specifications

Speed DDR4 2400 Unit

Parameter Symbol Min Max

Average Clock Period

tCK 0.833 <0.938 ns

CK high-level width

tCH 0.48 0.52 tCK

CK low-level width tCL 0.48 0.52 tCK

DQS, /DQS to DQ skew, per group, per

access

tDQSQ - 0.16

tCK(avg)

DQ output hold time from DQS, /DQS

tQH 0.76 -

tCK(avg)

DQS_t and DQS_c low-impedance time

(Referenced from RL-1)

tLZ(DQS) -300 150

DQS_t and DQS_c high-impedance time

(Referenced from RL+BL/2)

tHZ(DQS) - 150

DQS_t, DQS_c falling edge setup time to

CK_t, CK_c rising edge

tDSS 0.18 - tCK

DQS_t, DQS_c falling edge hold time

from CK_t, CK_c rising edge

tDSH 0.18

tCK

DQS, /DQS Read preamble

tRPRE

0.9 - tCK

1.8 tCK

DQS, /DQS differential Read postamble

tRPST 0.33 - tCK

DQS, /DQS Write preamble

tWPRE

0.9 - tCK

1.8 NA tCK

DQS, /DQS Write postamble

tWPST 0.33 - tCK

DQS, /DQS differential input low pulse

width

tDQSL 0.46 0.54 tCK

DQS, /DQS differential input high pulse

width

tDQSH 0.46 0.54 tCK

DQS, /DQS rising edge to CK, /CK rising

edge

tDQSS -0.27 +0.27 tCK

DQS, /DQS falling edge setup time to

CK, /CK rising edge

tDSS

0.18 -

tCK

DQS, /DQS falling edge hold time to CK,

/CK rising edge

tDSH 0.18 - tCK

Delay from start of internal write

transaction to internal read com-mand for

different bank group

tWTR_S

max (2nCK, 2.5ns) -

Delay from start of internal write

transaction to internal read com-mand for

same bank group

tWTR_L

max (4nCK,7.5ns)

Write recovery time tWR

15 -

Mode register set command cycle time

tMRD 8 - nCK

CAS_n to CAS_n command delay for

same bank group

tCCD_L

max(5 nCK, 5 ns)

- nCK

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

AQD-D4U16E24-SE

Mfr. #:

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Manufacturer:

Advantech

Description:

Memory Modules 16G ECC DDR4-2400 1GX8 1.2V SAM

Lifecycle:

New from this manufacturer.

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