1/12August 2004
■ HIGH SPEED:
t
PD
=4.4ns (TYP.) at V
CC
= 3.3V
■ 5V TOLERANT INPUTS
■ POWER-DOWN PROTECTION ON INPUTS
■ INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
■ LOW POWER DISSIPATION:
I
CC
= 2 µA (MAX.) at T
A
=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 126
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX126 is a low voltage CMOS QUAD
BUS BUFFERs fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This device requires the 3-STATE control input G
to be set low to place the output go in to the high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V. It combines high speed
performance with the true CMOS low power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX126
LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX126MTR
TSSOP 74LVX126TTR
TSSOPSOP
Rev. 2
