NCP382LD15AAR2G

NCP382
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7
FUNCTIONAL DESCRIPTION
Overview
The NCP382 is a dual high side power distribution
switches designed to protect the input supply voltage in case
of heavy capacitive loads, short circuit or over current. In
addition, the high side MOSFETs are turned off during
undervoltage or thermal shutdown condition. Thanks to the
soft start circuitry, NCP382 is able to limit large current and
voltage surges.
Overcurrent Protection
NCP382 switches into a constant current regulation mode
when the output current is above the I
OCP
threshold.
Depending on the load, the output voltage is decreased
accordingly.
In case of hot plug with heavy capacitive load, the
output voltage is brought down to the capacitor voltage.
The NCP382 will limit the current to the I
OCP
threshold
value until the charge of the capacitor is completed.
VOUTX
IOCP
IOUTX
Drop due to
capacitor charge
Figure 6. Heavy Capacitive Load
In case of overload, the current is limited to the I
OCP
value and the voltage value is reduced according to the
load by the following relation:
V
OUTX
+ R
LOAD2
I
OCP
(eq. 1)
VOUTX
IOCP
IOUTX
IOCP x RLOAD
Figure 7. Overload
In case of short circuit or huge load, the current is
limited to the I
OCP
value within T
DET
time until the
short condition is removed. If the output remains
shorted or tied to a very low voltage, the junction
temperature of the chip exceeds T
SDOCP
value and the
device enters in thermal shutdown (MOSFET is
turned−off).
VOUTX
IOCP
IOUTX
Thermal
Regulation
Threshold
Timer
Regulation
Mode
TREGTOCP
Figure 8. Short−Circuit
Then, the device enters in timer regulation mode, described
in 2 phases:
Off−phase: Power MOSFET is off during T
OCP
to allow
the die temperature to drop.
On−phase: regulation current mode during T
REG.
The
current is regulated to the I
OCP
level.
The timer regulation mode allows the device to handle
high thermal dissipation (in case of short circuit for
example) within temperature operating condition.
NCP382 stays in on−phase/off−phase loop until the over
current condition is removed or enable pin is toggled.
Remark: other regulation modes can be available for
different applications. Please contact our On Semiconductor
representative for availability.
FLAG Indicator
The FLAG pin is an open−drain MOSFET asserted low
during overcurrent or overtemperature conditions. When an
overcurrent fault is detected on the power path, FLAG
pin
is asserted low at the end of the associate deglitch time
(TFOCP). Thanks to this feature, the FLAG
pin is not tied
low during the charge of a heavy capacitive load or a voltage
transient on output. The FLAG
pin remains low until the
fault is removed. Then, the FLAG
pin goes high at the end
of T
FGL
Undervoltage Lock−out
Thanks to a built−in under voltage lockout (UVLO)
circuitry, the output remains disconnected from input until
V
IN
voltage is above V
UVLO
. This circuit has a V
HYST
hysteresis witch provides noise immunity to transient
condition.
Thermal Sense
Thermal shutdown turns off the power MOSFET if the die
temperature exceeds T
SD
. A built-in hysteresis prevents the
part from turning on until the die temperature cools at
TRSD.
NCP382
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Enable Input
Enable pin must be driven by a logic signal (CMOS or
TTL compatible) or connected to the GND or VIN. A logic
low on ENX
or high on ENX turns−on the device. A logic
high on ENX
or low on ENX turns off device and reduces
the current consumption down to I
INOFF
.
Blocking Control
The blocking control circuitry switches the bulk of the
power MOS. When the part is off, the body diode limits the
leakage current I
REV
from OUTX to IN. In this mode, anode
of the body diode is connected to IN pin and cathode is
connected to OUTX pin. In operating condition, anode of
the body diode is connected to OUTX pin and cathode is
connected to IN pin preventing the discharge of the power
supply.
APPLICATION INFORMATION
Power Dissipation
The junction temperature of the device depends on
different contributing factors such as board layout, ambient
temperature, device environment, etc... Yet, the main
contributor in term of junction temperature is the power
dissipation of the power MOSFET. Assuming this, the
power dissipation and the junction temperature in normal
mode can be calculated with the following equations:
P
D
+ R
DS(on)
ǒ
ǒ
I
OUT1
Ǔ
2
)
ǒ
I
OUT2
Ǔ
2
Ǔ (eq. 2)
P
D
= Power dissipation (W)
R
DS(on)
= Power MOSFET on resistance (W)
I
OUTx
= Output current in channel X (A)
T
J
+ P
D
R
qJA
) T
A
(eq. 3)
T
J
= Junction temperature (°C)
R
q
JA
= Package thermal resistance (°C/W)
T
A
= Ambient temperature (°C)
Power dissipation in regulation mode can be calculated by
taking into account the drop V
IN
−V
OUTX
link to the load by
the following relation:
P
D
+
ǒ
ǒ
V
IN
* R
LOAD1
I
OCP
Ǔ
)
ǒ
V
IN
* R
LOAD2
I
OCP
Ǔ
Ǔ
(eq. 4)
I
OCP
P
D
= Power dissipation (W)
V
IN
= Input Voltage (V)
R
LOADX
= Load Resistance on channel X (W)
I
OCP
= Output regulated current (A)
PCB Recommendations
The NCP382 integrates two PMOS FET rated up to 2 A,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. The DFN8 PAD1 must
be connected to ground plane to increase the heat transfer if
necessary. Of course, in any case, this pad must not connect
to any other potential. By increasing PCB area, the R
q
JA
of
the package can be decreased, allowing higher current.
NCP382
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9
Figure 9. USB Host Typical Application

NCP382LD15AAR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Switch ICs - Power Distribution DUAL OVER CURRENT PROTECTION
Lifecycle:
New from this manufacturer.
Delivery:
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