LTC3604IUD#PBF Datasheet LTC3604IMSE#PBF, LTC3604EMSE#TRPBF, LTC3604EUD#TRPBF | P13-P15

LTC3604

3604fa

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3604 F02

OUT

SGND

LTC3604

Figure 2. Optional Feedforward Capacitor

Figure 3. Compensation Components

ITH

COMP

14k

COMP

150pF

BYP

3604 F03

SGND

LTC3604

APPLICATIONS INFORMATION

To improve the frequency response of the main control

loop a feedforward capacitor, C

, may be used as shown

in Figure 2.

tion, but the switching frequency will decrease from its

programmed value. This is an acceptable result in many

applications, so this constraint may not be of critical

importance in most cases, and high switching frequen-

cies may be used in the design without any fear of severe

consequences. As the sections on Inductor and Capacitor

Selection show, high switching frequencies allow the use

of smaller board components, thus reducing the footprint

of the application circuit.

Internal/External Loop Compensation

The LTC3604 provides the option to use a fixed internal

loop compensation network to reduce both the required

external component count and design time. The internal

loop compensation network can be selected by connect-

ing the ITH pin to the INTV

pin. To ensure stability, it

is recommended that the output capacitance be at least

47µF when using internal compensation. Alternatively,

the user may choose specific external loop compensation

components to optimize the main control loop transient

response as desired. External loop compensation is chosen

by simply connecting the desired network to the ITH pin.

Suggested compensation component values are shown in

Figure 3. For a 2MHz application, an R-C network of 150pF

and 14kΩ provides a good starting point. The bandwidth

of the loop increases with decreasing C. If R is increased

by the same factor that C is decreased, the zero frequency

will be kept the same, thereby keeping the phase the same

in the most critical frequency range of the feedback loop.

A 10pF bypass capacitor on the ITH pin is recommended

for the purposes of filtering out high frequency coupling

from stray board capacitance. In addition, a feedforward

capacitor C

can be added to improve the high frequency

response, as previously shown in Figure 2. Capacitor C

provides phase lead by creating a high frequency zero

with R1 which improves the phase margin.

Minimum Off-Time/On-Time Considerations

The minimum off-time is the smallest amount of time that

the LTC3604 can turn on the bottom power MOSFET, trip

the current comparator and turn the power MOSFET back

off. This time is typically 40ns. For the controlled on-time

current mode control architecture, the minimum off-time

limit imposes a maximum duty cycle of:

(MAX)

=1– f • t

OFF(MIN)

( )

where f is the switching frequency and t

OFF(MIN)

is the

minimum off-time. If the maximum duty cycle is surpassed,

due to a dropping input voltage for example, the output

will drop out of regulation. The minimum input voltage to

avoid this dropout condition is:

IN(MIN)

OUT

1− f • t

OFF(MIN)

( )

Conversely, the minimum on-time is the smallest dura-

tion of time in which the top power MOSFET can be in

its “on” state. This time is typically 20ns. In continuous

mode operation, the minimum on-time limit imposes a

minimum duty cycle of:

(MIN)

= f • t

ON(MIN)

( )

where t

ON(MIN)

is the minimum on-time. As the equation

shows, reducing the operating frequency will alleviate the

minimum duty cycle constraint.

In the rare cases where the minimum duty cycle is

surpassed, the output voltage will still remain in regula-

LTC3604

3604fa

For more information www.linear.com/LTC3604

APPLICATIONS INFORMATION

Checking Transient Response

The regulator loop response can be checked by observing

the response of the system to a load step. When config-

ured for external compensation, the availability of the

ITH pin not only allows optimization of the control loop

behavior but also provides a DC coupled and AC filtered

closed-loop response test point. The DC step, rise time,

and settling behavior at this test point reflect the system’s

closed-loop response. Assuming a predominantly second

order system, the phase margin and/or damping factor can

be estimated by observing the percentage of overshoot

seen at this pin. The ITH external components shown in

Figure 3 will provide an adequate starting point for most

applications. The series R-C filter sets the pole-zero loop

compensation. The values can be modified slightly, from

approximately 0.5 to 2 times their suggested values, to

optimize transient response once the final PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because their various types and values determine

the loop feedback factor gain and phase. An output cur-

rent pulse of 20% to 100% of full load current with a rise

time of 1µs to 10µs will produce output voltage and ITH

pin waveforms that will give a sense of the overall loop

stability without breaking the feedback loop

When observing the response of V

OUT

to a load step, the

initial output voltage step may not be within the bandwidth

of the feedback loop. As a result, the standard second

order overshoot/DC ratio cannot be used to estimate

phase margin. The output voltage settling behavior is

related to the stability of the closed-loop system and will

demonstrate the actual overall supply performance. For

a detailed explanation of optimizing the compensation

components, including a review of control loop theory,

refer to Linear Technology Application Note 76. As shown

in Figure 2 a feedforward capacitor, C

, may be added

across feedback resistor R1 to improve the high frequency

response of the system. Capacitor C

provides phase lead

by creating a high frequency zero with R1.

In some applications severe transients can be caused by

switching in loads with large (>10µF) input capacitors. The

discharged input capacitors are effectively put in parallel

with C

OUT

, causing a rapid drop in V

OUT

. No regulator can

deliver enough current to prevent this output droop if the

switch connecting the load has low resistance and is driven

quickly. The solution is to limit the turn-on speed of the

load switch driver. A Hot Swap



controller is designed

specifically for this purpose and usually incorporates cur-

rent limit, short-circuit protection and soft-start functions.

MODE/SYNC Operation

The MODE/SYNC pin is a multipurpose pin allowing both

mode selection and operating frequency synchronization.

Connecting this pin to INTV

enables Burst Mode operation

for superior efficiency at low load currents at the expense

of slightly higher output voltage ripple. When the MODE/

SYNC pin is pulled to ground, forced continuous mode

operation is selected creating the lowest fixed output ripple

at the expense of light load efficiency.

The LTC3604 will detect the presence of the external clock

signal on the MODE/SYNC pin and synchronize the internal

oscillator to the phase and frequency of the incoming clock.

The presence of an external clock will place the LTC3604

into forced continuous mode operation.

Output Voltage Tracking and Soft-Start

The LTC3604 allows the user to control the output volt-

age ramp rate by means of the TRACK/SS pin. From 0V

to 0.6V the TRACK/SS pin will override the internal refer-

ence input to the error amplifier forcing regulation of the

feedback voltage to that seen at the TRACK/SS pin. When

the voltage at the TRACK/SS pin rises above 0.6V, tracking

is disabled and the feedback voltage will be regulated to

the internal reference voltage.

The voltage at the TRACK/SS pin may be driven from an

external source, or alternatively, the user may leverage the

internal 1.4µA pull-up current on TRACK/SS to implement

a soft-start function by connecting a capacitor from the

TRACK/SS pin to ground. The relationship between output

rise time and TRACK/SS capacitance is given by:

= 430,000 × C

TRACK/SS

A default internal soft-start timer forces a minimum soft-

start time of 400µs by overriding the TRACK/SS pin input

LTC3604

3604fa

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PGOOD

VOLTAGE

OUT

–8% –5% 5% 8%

3604 F04

NOMINAL OUTPUT

Figure 4. PGOOD Pin Behavior

APPLICATIONS INFORMATION

during this time period. Hence, capacitance values less

than approximately 1000pF will not significantly affect

soft-start behavior.

When using the TRACK/SS pin, the regulator defaults to

Burst Mode operation until the output exceeds 80% of

its final value (V

> 0.48V). Once the output reaches this

voltage, the operating mode of the regulator switches to

the mode selected by the MODE/SYNC pin as described

above. During normal operation, if the output drops below

10% of its final value (as it may when tracking down, for

instance), the regulator will automatically switch to Burst

Mode operation to prevent inductor saturation and improve

TRACK/SS pin accuracy.

Output Power Good

The PGOOD output of the LTC3604 is driven by a 15Ω

(typical) open-drain pull-down device. This device will be

turned off once the output voltage is within ±5% (typical) of

the target regulation point allowing the voltage at PGOOD

to rise via an external pull-up resistor (100k typical). If the

output voltage exits a ±8% (typical) regulation window

around the target regulation point the open-drain output

will pull down with 15Ω output resistance to ground, thus

dropping the PGOOD pin voltage. A filter time of 40µs

(typical) acts to prevent unwanted PGOOD output changes

during V

OUT

transient events. As a result, the output voltage

must be within the target regulation window of ±5% for

40µs before the PGOOD pin is pulled high. Conversely, the

output voltage must exit the ±8% regulation window for

40µs before the PGOOD pin pulls to ground (see Figure 4).

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

% Efficiency = 100% – (L1 + L2 + L3 +…)

where L1, L2, etc. are the individual loss terms as a per-

centage of input power.

Although all dissipative elements in the circuit produce

losses, three main sources account for the majority of the

losses in the LTC3604: 1) I

R loss, 2) switching losses

and quiescent current loss, 3) transition losses and other

system losses.

1. I

R loss is calculated from the DC resistances of the

internal switches, R

, and external inductor, R

In continuous mode, the average output current will

flow through inductor L but is “chopped” between the

internal top and bottom power MOSFETs. Thus, the

series resistance looking into the SW pin is a function

of both the top and bottom MOSFET’s R

DS(ON)

and the

duty cycle (DC) as follows:

= (R

DS(ON)TOP

)(DC) + (R

DS(ON)BOT

)(1 – DC)

The R

DS(ON)

for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics

curves. Thus to obtain I

R loss:

“I

R LOSS” = I

OUT

· (R

+ R

)

2. The internal LDO supplies the power to the INTV

rail.

The total power loss here is the sum of the switching

losses and quiescent current losses from the control

circuitry.

Each time a power MOSFET gate is switched from low

to high to low again, a packet of charge dQ moves

from V

to ground. The resulting dQ/dt is a current

out of INTV

that is typically much larger than the DC

control bias current. In continuous mode, I

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Description:

Switching Voltage Regulators 2.5A, 15V Mono Sync Buck Reg

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