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71V321L25JI

P1-P3P4-P6P7-P9P10-P12P13-P15
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part numbers indicates power rating (S or L).
Symbol Parameter
71V321X25
Com'l & Ind
71V321X35
Com'l & Ind
71V321X55
Com'l & Ind
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 25
____
35
____
55
____
ns
t
EW
Chip Enable to End-of-Write 20
____
30
____
40
____
ns
t
AW
Address Valid to End-of-Write 20
____
30
____
40
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 20
____
30
____
40
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 12
____
20
____
20
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
30 ns
t
DH
Data Hold Time
(3)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
15
____
30 ns
t
OW
Output Active from End-of-Write
(1,2)
0
____
0
____
0
____
ns
3026 tbl 10
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
8
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)
(1,5)
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)
(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
t
WC
ADDRESS
OE
CE
R/W
DATA
OUT
DATA
IN
t
AS
t
WR
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(4) (4)
t
WZ
t
HZ
3026 drw 08
(6)
(7)
(7)
(3)
(7)
t
WC
ADDRESS
CE
R/W
DATA
IN
t
AS
t
EW
t
WR
t
DW
t
DH
t
AW
3026 drw 09
(6) (2)
(3)
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
71V321X25
Com'l & Ind
71V321X35
Com'l & Ind
71V321X55
Com'l & Ind
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY Timing
t
BAA
BUSY Access Time from Address
____
20
____
20
____
30 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20
____
30 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20
____
30 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
30 ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60
____
80 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
____
65 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
30
____
30
____
45 ns
3026 tbl 11
Timing Waveform of Write with Port-to-Port Read and BUSY
(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port “A” may be either the left or right port. Port “B” is opposite from port “A”.
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN "A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/W
"A"
BUSY
"B"
t
APS
3026 drw 10
(1)
t
BAA
P1-P3P4-P6P7-P9P10-P12P13-P15

71V321L25JI

Mfr. #:
Buy 71V321L25JI
Manufacturer:
IDT
Description:
SRAM 2Kx8 ASYNCHRONOUS 3.3V DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
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