LTC4053-4.2
13
4053fa
Regardless of mode, the voltage at the PROG pin is
proportional to the current being delivered to the battery.
Power Dissipation
The conditions that cause the LTC4053 to reduce charge
current due to the thermal protection feedback can be
approximated by considering the power dissipated in the
IC. For high charge currents, the LTC4053 power dissipa-
tion is approximately:
P
D
= (V
CC
– V
BAT
) • I
BAT
where P
D
is the power dissipated, V
CC
is the input supply
voltage, V
BAT
is the battery voltage, and I
BAT
is the battery
charge current. It is not necessary to perform any worst-
case power dissipation scenarios because the LTC4053
will automatically reduce the charge current to maintain
the die temperature at approximately 105°C. However, the
approximate ambient temperature at which the thermal
feedback begins to protect the IC is:
T
A
= 105°C – P
D
θ
JA
T
A
= 105°C – (V
CC
– V
BAT
) • I
BAT
θ
JA
Example: Consider an LTC4053 operating from a 5V wall
adapter providing 1.2A to a 3.75V Li-Ion battery. The
ambient temperature above which the LTC4053 will begin
to reduce the 1.2A charge current is approximately:
T
A
= 105°C – (5V – 3.75V) • 1.2A • 40°C/W
T
A
= 105°C – 1.5W • 40°C/W = 105°C – 60°C = 45°C
The LTC4053 can be used above 45°C, but the charge
current will be reduced below 1.2A. The approximate
charge current at a given ambient temperature can be
approximated by:
I
CT
VV
BAT
A
CC BAT JA
=
°105
(– )θ
Consider the above example with an ambient temperature
of 55°C. The charge current will be reduced to approxi-
mately:
I
CC
VVCW
C
CA
A
BAT
=
°°
°
=
°
°
=
105 55
5 3 75 40
50
50
1
(–. ) / /
APPLICATIO S I FOR ATIO
WUUU
Furthermore, the voltage at the PROG pin will change
proportionally with the charge current as discussed in the
Programming Charge Current section.
It is important to remember that LTC4053 applications do
not need to be designed for worst-case thermal conditions
since the IC will automatically reduce power dissipation
when the junction temperature reaches approximately
105°C.
Board Layout Considerations
The ability to deliver maximum charge current under all
conditions require that the exposed metal pad on the
backside of the LTC4053 package be soldered to the PC
board ground. Correctly soldered to a 2500mm
2
double-
sided 1oz. copper board the LTC4053 has a thermal
resistance of approximately 40°C/W. Failure to make
thermal contact between the exposed pad on the backside
of the package and the copper board will result in thermal
resistances far greater than 40°C/W. As an example, a
correctly soldered LTC4053 can deliver over 1250mA to a
battery from a 5V supply at room temperature. Without a
backside thermal connection, this number could drop to
less than 500mA.
V
CC
Bypass Capacitor
Many types of capacitors can be used for input bypassing.
However, caution must be exercised when using multi-
layer ceramic capacitors. Because of the self resonant and
high Q characteristics of some types of ceramic capaci-
tors, high voltage transients can be generated under some
start-up conditions, such as connecting the charger input
to a hot power source. For more information refer to
Application Note 88.
Stability
The constant-voltage mode feedback loop is stable
without any compensation provided that a battery is
connected. However, a 1µF capacitor with a 1 series
resistor to GND is recommended at the BAT pin to keep
ripple voltage low when the battery is disconnected.
In the constant-current mode it is the PROG pin that is in
the feedback loop and not the battery. The constant-
current mode stability is affected by the impedance at the
LTC4053-4.2
14
4053fa
PROG pin. With no additional capacitance on the PROG
pin, stability is acceptable with program resistor values as
high as 50k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 500kHz.
Therefore, if the PROG pin is loaded with a capacitance, C,
the following equation should be used to calculate the
maximum resistance value for R
PROG
:
R
PROG
< 1/(6.283 • 5 × 10
5
• C)
5
7
R
PROG
C
FILTER
CHARGE
CURRENT
MONITOR
CIRCUITRY
10k
LTC4053
4053 F05
GND
PROG
Figure 5. Isolating Capacitive Load on PROG Pin and Filtering
APPLICATIO S I FOR ATIO
WUUU
Average, rather than instantaneous, battery current may
be of interest to the user. For example, if a switching power
supply operating in low-current mode is connected in
parallel with the battery the average current being pulled
out of the BAT pin is typically of more interest than the
instantaneous current pulses. In such a case, a simple RC
filter can be used on the PROG pin to measure the average
battery current as shown in Figure 5. A 10k resistor is
added between the PROG pin and the filter capacitor and
monitoring circuit to ensure stability.
PACKAGE DESCRIPTIO
U
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
LTC4053-4.2
15
4053fa
PACKAGE DESCRIPTIO
U
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
MSOP (MSE) 0802
0.53 ± 0.01
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.13 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.50
(.0197)
BSC
12
3
45
4.90 ± 0.15
(1.93 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910
10
1
7
6
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010)
0
° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
2.083 ± 0.102
(.082 ± .004)
2.794 ± 0.102
(.110 ± .004)
0.50
(.0197)
BSC
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.83 ± 0.102
(.072 ± .004)
2.06 ± 0.102
(.081 ± .004)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4053EDD-4.2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management USB Li-Ion Battery Charger in DFN
Lifecycle:
New from this manufacturer.
Delivery:
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