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PRMD2Z

P1-P3P4-P6P7-P9P10-P12P13-P15
PRMD2
50 V, 100 mA NPN/PNP Resistor-Equipped double
Transistors (RET)
14 June 2017 Product data sheet
1. General description
NPN/PNP Resistor-Equipped double Transistors (RET) in a leadless ultra small DFN1412-6
(SOT1268) Surface-Mounted Device (SMD) plastic package.
2. Features and benefits
• 100 mA output current capability
• Built-in bias resistors
• Simplifies circuit design
• Reduces component count
• Reduces pick and place costs
• Low package height of 0.5 mm
• AEC-Q101 qualified
3. Applications
• Digital applications
• Cost-saving alternative to BC847/BC857 series in digital applications
• Control of IC inputs
• Switching loads
4. Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Per transistor, for the PNP transistor with negative polarity
V
CEO
collector-emitter
voltage
open base - - 50 V
I
O
output current - - 100 mA
h
FE
DC current gain V
CE
= 5 V; I
C
= 5 mA; T
amb
= 25 °C 60 - -
R1 bias resistor 1 [1] 15.4 22 28.6 kΩ
R2/R1 bias resistor ratio [1] 0.8 1 1.2
[1] See section "Test information" for resistor calculation and test conditions.
Nexperia
PRMD2
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
PRMD2 All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet 14 June 2017 2 / 15
5. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 GND1 GND (emitter) TR1
2 I1 input ( base) TR1
3 O2 output (collector) TR2
4 GND2 GND (emitter) TR2
5 I2 input ( base) TR2
6 O1 output (collector) TR1
7 O1 output (collector) TR1
8 O2 output (collector) TR2
Transparent top view
1 6
7
8
2
3
5
4
DFN1412-6 (SOT1268)
O1 I2 GND2
GND1
I1 O2
R2
TR1
TR2
R1
R2 R1
aaa-007379
6. Ordering information
Table 3. Ordering information
PackageType number
Name Description Version
PRMD2 DFN1412-6 plastic thermal enhanced ultra thin small outline package; no
leads; 6 terminals; body: 1.4 mm x 1.2 mm x 0.47 mm
SOT1268
7. Marking
Table 4. Marking codes
Type number Marking code
PRMD2 B4
Nexperia
PRMD2
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
PRMD2 All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet 14 June 2017 3 / 15
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor, for the PNP transistor with negative polarity
V
CBO
collector-base voltage open emitter - 50 V
V
CEO
collector-emitter voltage open base - 50 V
V
EBO
emitter-base voltage open collector - 10 V
V
I
input voltage -10 40 V
I
O
output current - 100 mA
P
tot
total power dissipation T
amb
≤ 25 °C [1] - 325 mW
Per device
P
tot
total power dissipation T
amb
≤ 25 °C [1] - 480 mW
T
j
junction temperature - 150 °C
T
amb
ambient temperature -55 150 °C
T
stg
storage temperature -65 150 °C
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
T
a
m
b
(
°
C
)
-75 17512525 75-25
aaa-024487
200
300
100
400
500
P
tot
(mW)
0
FR4 PCB, standard footprint
Fig. 1. Per device: Power derating curve
P1-P3P4-P6P7-P9P10-P12P13-P15

PRMD2Z

Mfr. #:
Buy PRMD2Z
Manufacturer:
Nexperia
Description:
Bipolar Transistors - BJT PRMD2/SOT1268 DFN1412-6
Lifecycle:
New from this manufacturer.
Delivery:
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