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10
SOFT START WITH PWM INPUT
Figure 7 below shows an example of a soft start when the device is powered up from standby with a PWM input. The PWM
signal here is at 100 Hz with a duty cycle of 30%. In this case the LED reaches 100% of its programmed value in 100 ms. This
time can be decreased if the PWM signal runs at a higher duty cycle.
100ms with 30% dimming duty cycle,
100Hz
Vfbp
Vfbn & LED
current
LED current reaches 100%
when Vfbn crosses Vfbp
Soft start with PWM dimming active
Vcomp is kept during
dimming off
PWMin and PWMout
Back light LED brightness gradually
rise to the set value
Figure 7. Soft Start with PWM Input
GATE AND PWMOUT PIN DRIVER CIRCUIT
Since external transistors are required for the boost converter and PWM dimming functions, the device contains an internal
10 V regulator to drive the gate of these transistors. In the case of the PWM transistor this also functions as a level translator
for the PWMin input pin. When selecting external components it is important that the transistor has enough gate drive to ensure
low R
DS(on)
for the expected current.
It should be noted that the internal 10 V regulator will start to drop when the VIN voltage is sufficiently low. When the V
IN
voltage is 8.5 V the gate drivers will be limited to around 7.7 V.
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VREF REFERENCE VOLTAGE
The device contains an accurate 5 V reference that can supply up to 10 mA and can be accessed through the VREF pin. It
can be used to program the LED feedback voltage by using a resistor divider on the FBP pin. This reference is only active when
STBY = low. When the device is in standby mode the VREF pin voltage will drop to 4.2 V typical with a minimum of 3.5 V.
The VREF will return to 5 V immediately when STBY is driven high.
MINIMUM ON & OFF TIME
If the steady state duty cycle and switching frequency combine to generate short Ton times (low VOUT/VIN converter ratio),
the converter will skip some cycles to regulate V
OUT
which will increase output voltage ripple. The timing limit is set by the
intrinsic loop propagation delay and the switching frequency will be limited by the minimum ON time and OFF time.
THE INDUCTOR SELECTION
For a given application, it is necessary to know the input voltage at the inductor (VIN
INDUCTOR
), the output current (I
OUT
)
set by RFBN and the voltage on the FBP pin, and the switching frequency (F
sw
). The inductor can be chosen using the formula
below:
L
max
t
1
2 F
sw
I
OUT
ǒ
V
IN
V
OUT
Ǔ
2
ǒ
V
OUT
* V
IN
Ǔ
(eq. 1)
The minimal inductor value is determined with the desired peak current flowing through the inductor. Using the chosen
inductor value the steady state duty cycle and peak inductor current can be calculated:
D +
2 L F
sw
I
OUT
ǒ
V
OUT
* V
IN
Ǔ
Ǹ
V
IN
(eq. 2)
And the inductor peak current is now:
I
peak
+
V
IN
D
L F
sw
+
2 I
OUT
(V
OUT
* V
IN
)
L F
sw
Ǹ
(eq. 3)
THE CURRENT SENSE RESISTOR
Set a current limit between 2 and 2.5 times the peak inductor current to account for inductor tolerance:
I
limit
+ 2.5 I
peak
(eq. 4)
The current limit reference fixed on the over-current protection comparator is V
CS
= 0.5 V and the resistance can be calculated
using following the equation:
R
CS
+
V
CS
2.5 I
peak
(eq. 5)
SLOPE COMPENSATION
After the current sense resistor is calculated additional calculations are needed for the external slope compensation ramp. Using
the R
SENSE
value the typical slope of the compensation ramp can be calculated:
Mramp +
1
2
R
SENSE
V
OUT
* V
IN
L
(eq. 6)
Using the typical value for , the external compensation resistor can be calculated as follows:
R
SC
+
M
RAMP
I
RAMP
(eq. 7)
The slope compensation ramp has an offset current, , which is used to calculate the peak ramp current and finally the adjusted
current sense resistor.
I
RAMP,peak
+ I
OFF
) D
I
RAMP
R
SW
(eq. 8)
R
CS
+
V
CS
* R
CS
I
RAMP,peak
I
limit
) I
RAMP,peak
(eq. 9)
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OUTPUT CAPACITOR and OUTPUT VOLTAGE RIPPLE
Calculating the output voltage ripple will size the output capacitor value. The output voltage ripple equation below takes
into account the parasitic impedance (ESR) of this output capacitor:
DV
COUT
+
I
OUT
ǒ
1 * D
2
Ǔ
C
OUT
F
sw
) ESR I
OUT
(eq. 10)
DV
COUT
+
I
OUT
C
OUT
F
sw
ǒ
1 *
I
peak
L F
sw
V
OUT
* V
IN
Ǔ
) ESR I
OUT
(eq. 11)
Without taking into account the ESR, the output capacitor becomes:
C
OUT
u
I
OUT
DV
OUT
F
sw
ǒ
1 *
I
peak
L F
sw
V
OUT
* V
IN
Ǔ
(eq. 12)
If the ESR value of the selected output capacitor is high, the voltage ripple will increase. The error due to the ESR can be
estimated follow the equation below:
DV
OUTESR
+ ESR I
peak
(eq. 13)
SIZING THE COMP PIN CAPACITOR
The transistor Q1 is turned ON (reset of the duty cycle) when the Vf of the output current amplifier reaches the control output
voltage V
c
. The control voltage V
c
is simply a reduced voltage out of the follower servicing the voltage on the COMP pin.
In steady state, at DT
sw
, the voltage at the current amplifier output is represented by the equation below:
V
C
+ I
peak
R
CS
G
i
(eq. 14)
V
comp
+ V
C
) V
OS
(eq. 15)
V
comp
= COMP pin output voltage
V
c
= Voltage Control of the transconductance amplifier
V
os
= voltage offset of the transconductance amplifier
V
f
+
V
IN
D R
CS
G
i
L F
sw
(eq. 16)
i + C
dv
dt
å C
comp
+
i
EA
t
rise
V
comp
+
i
EA
t
rise
V
c
) V
os
(eq. 17)
i
EA
= 4 mA error amplifier output current capability
t
rise
= soft start time
V
os
= 0.9 V voltage offset due to the follower
So
C
comp
t
i
EA
t
rise
V
C
) V
OS
(eq. 18)
C
comp
+ 0.7
i
EA
30 ms
V
IN
D R
CS
G
L
L F
sw
) V
OS
(eq. 19)
During the soft start and with the dimming function activated, the COMP pin voltage is rising during 30 ms within the 100 ms
soft start time so V
comp
holds for another during 70 ms afterwards. Attention needs to be brought to the DC voltage rating. As
the capacitor value decreases and the DC voltage increases, the value chosen needs to be

NCS29001DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LED Lighting Drivers HV LED DRIVER
Lifecycle:
New from this manufacturer.
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