TC7136/TC7136A
DS21461C-page 10 © 2005 Microchip Technology Inc.
4.0 ANALOG SECTION
In addition to the basic integrate and de-integrate dual
slope cycles discussed above, the TC7136 and
TC7136A designs incorporate an "integrator output
zero cycle" and an "auto-zero cycle." These additional
cycles ensure the integrator starts at 0V (even after a
severe over range conversion) and that all offset volt-
age errors (buffer amplifier, integrator and comparator)
are removed from the conversion. A true digital zero
reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
1. Integrator output zero phase
2. Auto-zero phase
3. Signal integrate phase
4. Reference de-integrate phase
4.1 Integrator Output Zero Phase
This phase ensures the integrator output is at 0V
before the system zero phase is entered. This ensures
that true system offset voltages will be compensated
for, even after an over range conversion. The count for
this phase is a function of the number of counts
required by the de-integrate phase. The count lasts
from 11 to 140 counts for non over range conversions
and from 31 to 640 counts for over range conversions.
4.2 Auto-Zero Phase
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal
analog gates. The internal nodes are shorted to analog
common (ground) to establish a zero input condition.
Additional analog gates close a feedback loop around
the integrator and comparator. This loop permits com-
parator offset voltage error compensation. The voltage
level established on C
AZ
compensates for device offset
voltages. The auto-zero phase residual is typically
10μV to 15μV.
The auto-zero duration is from 910 to 2900 counts for
non over range conversions and from 300 to 910
counts for over range conversions.
4.3 Signal Integration Phase
The auto-zero loop is entered and the internal differen-
tial inputs connect to V
IN
+ and V
IN
-. The differential
input signal is integrated for a fixed time period. The
TC7136/A signal integration period is 1000 clock peri-
ods or counts. The externally set clock frequency is
divided by four before clocking the internal counters.
The integration time period is:
EQUATION 4-1:
The differential input voltage must be within the device
Common mode range when the converter and mea-
sured system share the same power supply common
(ground). If the converter and measured system do not
share the same power supply common, V
IN
- should be
tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication, in that
signals less than 1LSB are correctly determined. This
allows precision null detection, limited only by device
noise and auto-zero residual offsets.
4.4 Reference Integrate Phase
The third phase is reference integrate or de-integrate.
V
IN
- is internally connected to analog common and
V
IN
+
is connected across the previously charged refer-
ence capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity
to cause the integrator output to return to zero. The
time required for the output to return to zero is propor-
tional to the input signal and is between 0 and 2000
internal clock periods. The digital reading displayed is:
EQUATION 4-2:
FIGURE 4-1: CONVERSION TIMING
DURING NORMAL
OPERATION
FIGURE 4-2: CONVERSION TIMING
DURING OVER RANGE
OPERATION
t
SI
= x 1000
4
F
OSC
Where F
OSC
= external clock frequency.
1000
V
IN
V
REF
----------------=
INT
DENT
ZI
AZ
4000
910-2900
1-2000
1000
11-140
AZ
4000
ZI
DEINT
INT
1000
2001-2090
31-640
300-910
© 2005 Microchip Technology Inc. DS21461C-page 11
TC7136/TC7136A
5.0 DIGITAL SECTION
The TC7136/A contains all the segment drivers neces-
sary to directly drive a 3-1/2 digit LCD. An LCD back-
plane driver is included. The backplane frequency is
the external clock frequency divided by 800. For three
conversions per second, the backplane frequency is
60Hz with a 5V nominal amplitude. When a segment
driver is in phase with the backplane signal, the seg-
ment is OFF. An out-of-phase segment drive signal
causes the segment to be ON, or visible. This AC drive
configuration results in negligible DC voltage across
each LCD segment, ensuring long LCD life. The polar-
ity segment driver is ON for negative analog inputs. If
V
IN
+ and V
IN
- are reversed, this indicator would
reverse.
On the TC7136/A, when the TEST pin is pulled to V+,
all segments are turned ON. The display reads -1888.
During this mode, the LCD segments have a constant
DC voltage impressed.
The display font and segment drive assignment are
shown in Figure 5-1.
FIGURE 5-1: DISPLAY FONT AND
SEGMENT ASSIGNMENT
5.1 System Timing
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The four-phase mea-
surement cycle takes a total of 4000 counts, or 16,000
clock pulses. The 4000 count cycle is independent of
input signal magnitude.
Each phase of the measurement cycle has the
following length:
1. Auto-zero phase: 3000 to 2900 counts
(1200 to 11,600 clock pulses)
2. Signal integrate: 1000 counts
(4000 clock pulses)
This time period is fixed. The integration period is:
EQUATION 5-1:
3. Reference integrate: 0 to 2000 counts
4. Zero integrator: 11 to 640 counts
The TC7136 is a drop-in replacement for the TC7126
and ICL7126. The TC7136A offers a greatly improved
internal reference temperature coefficient. Minor com-
ponent value changes are required to upgrade existing
designs and improve the noise performance.
6.0 COMPONENT VALUE
SELECTION
6.1 Auto-Zero Capacitor (C
AZ
)
The C
AZ
capacitor size has some influence on system
noise. A 0.47μF capacitor is recommended for 200mV
full scale applications, where 1LSB is 100μV. A 0.1μF
capacitor is adequate for 2V full scale applications. A
Mylar type dielectric capacitor is adequate.
6.2 Reference Voltage Capacitor
(C
REF
)
The reference voltage, used to ramp the integrator out-
put voltage back to zero during the reference integrate
phase, is stored on C
REF
. A 0.1μF capacitor is accept-
able when V
REF
- is tied to analog common. If a large
Common mode voltage exists (V
REF
- analog com-
mon) and the application requires a 200mV full scale,
increase C
REF
to 1μF. Rollover error will be held to less
than 0.5 count. A Mylar type dielectric capacitor is
adequate.
6.3 Integrating Capacitor (C
INT
)
C
INT
should be selected to maximize integrator output
voltage swing without causing output saturation. Ana-
log common will normally supply the differential voltage
reference in this case, a ±2V full scale integrator output
swing is satisfactory. For 3 readings per second
(F
OSC
= 48kHz), a 0.047μF value is suggested. For
one reading per second, 0.15μF is recommended. If a
different oscillator frequency is used, C
INT
must be
changed in inverse proportion to maintain the nominal
±2V integrator swing.
Note: Do not leave the display in this mode for
more than several minutes. LCDs may be
destroyed if operated with DC levels for
extended periods.
Display Font
1000's 100's 10's 1's
Where:
t
SI
= 4000
1
F
OSC
F
OSC
is the externally set clock frequency.
TC7136/TC7136A
DS21461C-page 12 © 2005 Microchip Technology Inc.
An exact expression for C
INT
is:
EQUATION 6-1:
C
INT
must have low dielectric absorption to minimize
rollover error. A polypropylene capacitor is
recommended.
6.4 Integrating Resistor (R
INT
)
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling cur-
rent is 6μA. The integrator and buffer can supply 1μA
drive currents with negligible linearity errors. R
INT
is
chosen to remain in the output stage linear drive
region, but not so large that PC board leakage currents
induce errors. For a 200mV full scale, R
INT
is 180kΩ. A
2V full scale requires 1.8MΩ (see Table 6-1).
TABLE 6-1:
Note: F
OSC
= 48kHz (3 reading per sec).
R
OSC
= 180kΩ, C
OSC
= 50pF.
6.5 Oscillator Components
C
OSC
should be 50pF. R
OSC
is selected from the
equation:
EQUATION 6-2:
Note that F
OSC
is ÷ 4 to generate the TC7136A's inter-
nal clock. The backplane drive signal is derived by
dividing F
OSC
by 800.
To achieve maximum rejection of 60Hz noise pickup,
the signal integrate period should be a multiple of
60Hz. Oscillator frequencies of 240kHz, 120kHz,
80kHz, 60kHz, 40kHz, etc. should be selected. For
50Hz rejection, oscillator frequencies of 200kHz,
100kHz, 66-2/3kHz, 50kHz, 40kHz, etc. would be suit-
able. Note that 40kHz (2.5 readings per second) will
reject both 50Hz and 60Hz.
6.6 Reference Voltage Selection
A full scale reading (2000 counts) requires the input
signal be twice the reference voltage.
Note: *V
REF
= 2V
REF.
In some applications, a scale factor other than unity
may exist between a transducer output voltage and the
required digital reading. Assume, for example, a pres-
sure transducer output for 2000 lb/in
2
is 400mV. Rather
than dividing the input voltage by two, the reference
voltage should be set to 200mV. This permits the trans-
ducer input to be used directly. The differential refer-
ence can also be used when a digital zero reading is
required, when V
IN
is not equal to zero. This is common
in temperature measuring instrumentation. A compen-
sating offset voltage can be applied between analog
common and V
IN
-. The transducer output is connected
between V
IN
+ and analog common.
Component
Value
Nominal Full Scale Voltage
200mV 2V
C
AZ
0.47μF 0.1μF
R
INT
180kΩ 1.8MΩ
C
INT
0.047μF 0.047μF
(4000)
1
F
OSC
C
INT
=
V
FS
R
INT
V
INT
Where:
F
OSC
=Clock frequency at Pin 38
V
FS
=Full scale input voltage
R
INT
= Integrating resistor
V
INT
= Desired full scale integrator output swing
Required Full Scale Voltage* V
REF
200mV 100mV
2V 1V
F
OSC
=
0.45
RC

TC7136CLW713

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IC ADC 3 1/2DGT LOW PWR 44-PLCC
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