PCA9515DP,118 Datasheet PCA9515DP,118, PCA9515D,118, PCA9515D,112 | P4-P6

Product data sheet Rev. 09 — 23 April 2009 4 of 16

NXP Semiconductors

PCA9515

C-bus repeater

6. Functional description

The PCA9515 BiCMOS integrated circuit contains two identical buffer circuits which

enable I

C-bus and similar bus systems to be extended without degradation of system

performance. (Refer to Figure 1 “Block diagram of PCA9515”.)

The PCA9515 BiCMOS integrated circuit contains two bidirectional open-drain buffers

speciﬁcally designed to support the standard low-level-contention arbitration of the

C-bus. Except during arbitration or clock stretching, the PCA9515 acts like a pair of

non-inverting, open-drain buffers, one for SDA and one for SCL.

6.1 Enable

The EN pin is active HIGH with an internal pull-up and allows the user to select when the

repeater is active. This can be used to isolate a badly behaved slave on power-up until

after the system power-up reset. It should never change state during an I

C-bus operation

because disabling during a bus operation will hang the bus and enabling part way through

a bus cycle could confuse the I

C-bus parts being enabled.

The enable pin (EN) should only change state when the global bus and the repeater port

are in an idle state to prevent system failures.

6.2 I

C-bus systems

As with the standard I

C-bus system, pull-up resistors are required to provide the logic

HIGH levels on the buffered bus. (Standard open-collector conﬁguration of the I

C-bus.)

The size of these pull-up resistors depends on the system, but each side of the repeater

must have a pull-up resistor. This part is designed to work with Standard-mode and

Fast-mode I

C-bus devices in addition to SMBus devices. Standard-mode I

C-bus devices

only specify 3 mA output drive; this limits the termination current to 3 mA in a generic

C-bus system where Standard-mode devices and multiple masters are possible. Under

certain conditions, higher termination currents can be used. Please see application note

AN255, “I

C/SMBus Repeaters, Hubs and Expanders”

for additional information on sizing

resistors and precautions when using more than one PCA9515 in a system or using the

PCA9515 in conjunction with the P82B96.

Product data sheet Rev. 09 — 23 April 2009 5 of 16

NXP Semiconductors

PCA9515

C-bus repeater

7. Application design-in information

A typical application is shown in Figure 4. In this example, the system master is running

on a 3.3 V I

C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz

unless the slave bus is isolated and then the master bus can run at 400 kHz. Master

devices can be placed on either bus.

The PCA9515 is 5 V tolerant so it does not require any additional circuitry to translate

between the different bus voltages.

When one side of the PCA9515 is pulled LOW by a device on the I

C-bus, a CMOS

hysteresis type input detects the falling edge and causes an internal driver on the other

side to turn on, thus causing the other side to also go LOW. The side driven LOW by the

PCA9515 will typically be at V

= 0.5 V.

In order to illustrate what would be seen in a typical application, refer to Figure 5 and

Figure 6. If the bus master in Figure 4 were to write to the slave through the PCA9515, we

would see the waveform shown in Figure 5 on Bus 0. This looks like a normal I

C-bus

transmission until the falling edge of the 8

clock pulse. At that point, the master releases

the data line (SDA) while the slave pulls it LOW through the PCA9515. Because the V

the PCA9515 is typically around 0.5 V, a step in the SDA will be seen. After the master

has transmitted the 9

clock pulse, the slave releases the data line.

On the Bus 1 side of the PCA9515, the clock and data lines would have a positive offset

from ground equal to the V

of the PCA9515. After the 8

clock pulse, the data line will

be pulled to the V

of the slave device that is very close to ground in our example.

It is important to note that any arbitration or clock stretching events on Bus 1 require that

the V

of the devices on Bus 1 be 70 mV below the V

of the PCA9515 (see V

−V

ILc

Section 9 “Static characteristics”) to be recognized by the PCA9515 and then transmitted

to Bus 0.

Fig 4. Typical application

002aae621

PCA9515

SDA0 SDA1

SCL0 SCL1

SDA

SCL

BUS

MASTER

400 kHz

SLAVE

100 kHz

SDA

SCL

bus 0 bus 1

5 V

3.3 V

Product data sheet Rev. 09 — 23 April 2009 6 of 16

NXP Semiconductors

PCA9515

C-bus repeater

8. Limiting values

Fig 5. Bus 0 waveform

clock pulse

of master

of PCA9515

002aae622

SCL

SDA

Fig 6. Bus 1 waveform

clock pulse

of slave

of PCA9515

002aae623

SCL

SDA

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Voltages with respect to GND.

Symbol Parameter Conditions Min Max Unit

supply voltage −0.5 +7 V

bus

voltage range I

C-bus SCL or SDA −0.5 +7 V

I DC current any pin - 50 mA

tot

total power dissipation - 100 mW

stg

storage temperature −55 +125 °C

amb

ambient temperature operating −40 +85 °C

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PCA9515DP,118

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Buy PCA9515DP,118

Manufacturer:

NXP Semiconductors

Description:

Interface - Signal Buffers, Repeaters I2C BUS REPEATER

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PCA9515DP,118

PCA9515DP,118

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