LTC4442EMS8E-1#TRPBF

LTC4442/LTC4442-1
10
4442fb
APPLICATIONS INFORMATION
Power Dissipation
To ensure proper operation and long-term reliability, the
LTC4442 must not operate beyond its maximum tem-
perature rating. Package junction temperature can be
calculated by:
T
J
= T
A
+ (P
D
)(θ
JA
)
where:
T
J
= Junction temperature
T
A
= Ambient temperature
P
D
= Power dissipation
θ
JA
= Junction-to-ambient thermal resistance
Power dissipation consists of standby, switching and
capacitive load power losses:
P
D
= P
DC
+ P
AC
+ P
QG
where:
P
DC
= Quiescent power loss
P
AC
= Internal switching loss at input frequency f
IN
P
QG
= Loss due turning on and off the external MOSFET
with gate charge Q
G
at frequency f
IN
The LTC4442 consumes very little quiescent current. The
DC power loss at V
LOGIC
= 5V and V
CC
= V
BOOST
− TS =
7V is only (730A)(5V) + (625A)(7V) = 8mW.
At a particular switching frequency, the internal power loss
increases due to both AC currents required to charge and
discharge internal nodal capacitances and cross-conduc-
tion currents in the internal logic gates. The sum of the
quiescent current and internal switching current with no
load are shown in the Typical Performance Characteristics
plot of Switching Supply Current vs Input Frequency.
The gate charge losses are primarily due to the large AC
currents required to charge and discharge the capacitance
of the external MOSFETs during switching. For identical
pure capacitive loads C
LOAD
on TG and BG at switching
frequency fi n, the load losses would be:
P
CLOAD
= (C
LOAD
)(f
IN
)[(V
BOOST
– TS)
2
+ (V
CC
)
2
]
In a typical synchronous buck confi guration, V
BOOST
TS
is equal to V
CC
– V
D
, where V
D
is the forward voltage
drop across the diode between V
CC
and BOOST. If this
drop is small relative to V
CC
, the load losses can be
approximated as:
P
CLOAD
≈ 2(C
LOAD
)(f
IN
)(V
CC
)
2
Unlike a pure capacitive load, a power MOSFETs gate
capacitance seen by the driver output varies with its V
GS
voltage level during switching. A MOSFETs capacitive load
power dissipation can be calculated using its gate charge,
Q
G
. The Q
G
value corresponding to the MOSFETs V
GS
value (V
CC
in this case) can be readily obtained from the
manufacturers Q
G
vs V
GS
curves. For identical MOSFETs
on TG and BG:
P
QG
≈ 2(V
CC
)(Q
G
)(f
IN
)
To avoid damaging junction temperatures due to power
dissipation, the LTC4442 includes a temperature monitor
that will pull BG and TG low if the junction temperature
exceeds 160°C. Normal operation will resume when the
junction temperature cools to less than 135°C.
Bypassing and Grounding
The LTC4442 requires proper bypassing on the V
LOGIC
, V
CC
and V
BOOST
– TS supplies due to its high speed switching
(nanoseconds) and large AC currents (Amperes). Careless
component placement and PCB trace routing may cause
excessive ringing and undershoot/overshoot.
LTC4442/LTC4442-1
11
4442fb
To obtain the optimum performance from the LTC4442:
A. Mount the bypass capacitors as close as possible
between the V
LOGIC
and GND pins, the V
CC
and GND
pins, and the BOOST and TS pins. The leads should
be shortened as much as possible to reduce lead
inductance.
B. Use a low inductance, low impedance ground plane
to reduce any ground drop and stray capacitance.
Remember that the LTC4442 switches greater than
5A peak currents and any signifi cant ground drop will
degrade signal integrity.
APPLICATIONS INFORMATION
C. Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for
the input pin and the output power stage.
D. Keep the copper traces between the driver output pins
and the load short and wide.
E. Be sure to solder the Exposed Pad on the back side of
the LTC4442 packages to the board. Correctly soldered
to a 2500mm
2
double-sided 1oz copper board, the
LTC4442 has a thermal resistance of approximately
40°C/W. Failure to make good thermal contact between
the exposed back side and the copper board will result
in thermal resistances far greater.
LTC4442/LTC4442-1
12
4442fb
PACKAGE DESCRIPTION
MSOP (MS8E) 0908 REV E
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.65
(.0256)
BSC
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
3
4
4.90 p 0.152
(.193 p .006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
7
6
5
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.52
(.0205)
REF
1.83 p 0.102
(.072 p .004)
2.06 p 0.102
(.081 p .004)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
2.083 p 0.102
(.082 p .004)
2.794 p 0.102
(.110 p .004)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
0.1016 p 0.0508
(.004 p .002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev E)

LTC4442EMS8E-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers Hi Speed Sync N-Ch MOSFET Drvrs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union