LT3575
13
3575f
Figure 5. Maximum Voltages for SW Pin Flyback WaveformFigure 4. Snubber Clamping
Figure 6. Good Snubber Diode Limits SW Pin Voltage Figure 7. Bad Snubber Diode Does Not Limit SW Pin Voltage
< 50V
< 55V
< 60V
V
SW
t
OFF
> 350ns
TIME
t
SP
< 150ns
3575 F05
100ns/DIV
10V/DIV
3575 F06
100ns/DIV
10V/DIV
3575 F07
3575 F04
L
S
D
R
CLAMP EITHER
ZENER OR RC
C
APPLICATIONS INFORMATION
LT3575
14
3575f
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the secondary
in particular exhibits an additional phenomenon. It forms
an inductive divider on the transformer secondary that
effectively reduces the size of the primary-referred
yback pulse used for feedback. This will increase the
output voltage target by a similar percentage. Note that
unlike leakage spike behavior, this phenomenon is load
independent. To the extent that the secondary leakage
inductance is a constant percentage of mutual inductance
(over manufacturing variations), this can be accommodated
by adjusting the R
FB
/R
REF
resistor ratio.
Winding Resistance Effects
Resistance in either the primary or secondary will reduce
overall efficiency (P
OUT
/P
IN
). Good output voltage
regulation will be maintained independent of winding
resistance due to the boundary mode operation of the
LT3575.
Bifi lar Winding
A bifi lar, or similar winding technique, is a good way to
minimize troublesome leakage inductances. However,
remember that this will also increase primary-to-secondary
capacitance and limit the primary-to-secondary breakdown
voltage, so, bifi lar winding is not always practical. The
Linear Technology applications group is available and
extremely qualifi ed to assist in the selection and/or design
of the transformer.
Setting the Current Limit Resistor
The maximum current limit can be set by placing a resistor
between the R
ILIM
pin and ground. This provides some
exibility in picking standard off-the-shelf transformers that
may be rated for less current than the LT3575’s internal
power switch current limit. If the maximum current limit
is needed, use a 10k resistor. For lower current limits, the
following equation sets the approximate current limit:
RAIk
IL IM L IM
=−+65 10 3 5 10
3
•(. )
The Switch Current Limit vs R
ILIM
plot in the Typical
Performance Characteristics section depicts a more
accurate current limit.
Undervoltage Lockout (UVLO)
The SHDN/UVLO pin is connected to a resistive voltage
divider connected to V
IN
as shown in Figure 8. The voltage
threshold on the SHDN/UVLO pin for V
IN
rising is 1.22V.
To introduce hysteresis, the LT3575 draws 2.8μA from the
SHDN/UVLO pin when the pin is below 1.22V. The hysteresis
is therefore user-adjustable and depends on the value of
R1. The UVLO threshold for V
IN
rising is:
V
VR R
R
µA R
IN UVL O RIS ING(, )
.•( )
.•=
+
+
122 1 2
2
28 1
The UVLO threshold for V
IN
falling is:
V
VR R
R
IN UVLO FALLING(, )
.•( )
=
+122 1 2
2
To implement external run/stop control, connect a small
NMOS to the UVLO pin, as shown in Figure 8. Turning the
NMOS on grounds the UVLO pin and prevents the LT3575
from operating, and the part will draw less than a 1μA of
quiescent current.
Figure 8. Undervoltage Lockout (UVLO)
LT3575
SHDN/UVLO
GND
R2
R1
V
IN
3575 F08
RUN/STOP
CONTROL
(OPTIONAL)
APPLICATIONS INFORMATION
LT3575
15
3575f
APPLICATIONS INFORMATION
schematics in the Typical Applications section for other
possible values). If too large of an R
C
value is used, the part
will be more susceptible to high frequency noise and jitter. If
too small of an R
C
value is used, the transient performance
will suffer. The value choice for C
C
is somewhat the inverse
of the R
C
choice: if too small a C
C
value is used, the loop
may be unstable, and if too large a C
C
value is used, the
transient performance will also suffer. Transient response
plays an important role for any DC/DC converter.
Design Example
The following example illustrates the converter design
process using LT3575.
Given the input voltage of 20V to 28V, the required output
is 5V, 1A.
V
IN(MIN)
= 20V, V
IN(MAX)
= 28V, V
OUT
= 5V, V
F
= 0.5V
and I
OUT
= 1A
1. Select the transformer turns ratio to accommodate
the output.
The output voltage is refl ected to the primary side by a
factor of turns ratio N. The switch voltage stress V
SW
is
expressed as:
N
N
N
VVNVVV
P
S
SW MAX IN OUT F
=
=+ +<
()
()50
Or rearranged to:
N
V
VV
IN MAX
OUT F
<
+
50
()
()
On the other hand, the primary side current is multiplied by
the same factor of N. The converter output capability is:
IDNI
D
NV V
VN
OUT MA X PK
OUT F
IN
()
.•( )
()
=−
=
+
+
08 1
1
2
(()VV
OUT F
+
Minimum Load Requirement
The LT3575 obtains output voltage information through
the transformer while the secondary winding is conducting
current. During this time, the output voltage (multiplied
times the turns ratio) is presented to the primary side of
the transformer. The LT3575 uses this refl ected signal to
regulate the output voltage. This means that the LT3575
must turn on every so often to sample the output voltage,
which delivers a small amount of energy to the output.
This sampling places a minimum load requirement on the
output of 1% to 2% of the maximum load.
A Zener diode with a Zener breakdown of 20% higher
than the output voltage can serve as a minimum load if
pre-loading is not acceptable. For a 5V output, use a 6V
Zener with cathode connected to the output.
BIAS Pin Considerations
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the V
IN
pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the V
IN
pin. In this condition, the
BIAS pin is regulated with an internal LDO to a voltage of
3V. By keeping the BIAS pin separate from the input voltage
at high input voltages, the physical size of the capacitors
can be minimized (the BIAS pin can then use a 6.3V or
10V rated capacitor).
Overdriving the BIAS Pin with a Third Winding
The LT3575 provides excellent output voltage regulation
without the need for an optocoupler, or third winding, but
for some applications with higher input voltages (>20V),
it may be desirable to add an additional winding (often
called a third winding) to improve the system effi ciency.
For proper operation of the LT3575, if a winding is used as
a supply for the BIAS pin, ensure that the BIAS pin voltage
is at least 3.15V and always less than the input voltage.
For a typical 24V
IN
application, overdriving the BIAS pin
will improve the effi ciency gain 4-5%.
Loop Compensation
The LT3575 is compensated using an external resistor-
capacitor network on the V
C
pin. Typical values are in
the range of R
C
= 50k and C
C
= 1.5nF (see the numerous

LT3575IFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Iso Fly Conv w/out an Opto-Coupler
Lifecycle:
New from this manufacturer.
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