LT3575
16
3575f
APPLICATIONS INFORMATION
The transformer turns ratio is selected such that the
converter has adequate current capability and a switch
stress below 50V. Table 6 shows the switch voltage stress
and output current capability at different transformer
turns ratio.
Table 6. Switch Voltage Stress and Output Current Capability vs
Turns-Ratio
N
V
SW(MAX)
AT V
IN(MAX)
(V)
I
OUT(MAX)
AT V
IN(MIN)
(A)
DUTY CYCLE
(%)
1:1 33.5 1.26 16~22
2:1 39 2.07 28~35
3:1 44.5 2.63 37~45
4:1 50 3.05 44~52
BIAS winding turns ratio is selected to program the BIAS
voltage to 3V~5V. The BIAS voltage shall not exceed the
input voltage.
The turns ratio is then selected as primary: secondary:
BIAS = 3:1:1.
2. Select the transformer primary inductance for target
switching frequency.
The LT3575 requires a minimum amount of time to sample
the output voltage during the off-time. This off-time,
t
OFF(MIN)
, shall be greater than 350ns over all operating
conditions. The converter also has a minimum current limit,
I
MIN
, of 400mA to help create this off-time. This defi nes
the minimum required inductance as defi ned as:
L
NV V
I
t
MIN
OUT F
MIN
OFF MIN
=
+()
()
The transformer primary inductance also affects the
switching frequency which is related to the output ripple. If
above the minimum inductance, the transformers primary
inductance may be selected for a target switching frequency
range in order to minimize the output ripple.
The following equation estimates the switching frequency.
f
tt
I
V
L
I
NV V
L
SW
ON OFF
PK
IN
PK
PS OUT F
=
+
=
+
+
11
()
Table 7.Switching Frequency at Different Primary
Inductance at I
PK
L (μH)
f
SW
AT V
IN(MIN)
(kHz)
f
SW
AT V
IN(MAX)
(kHz)
15 174 205
30 87 103
60 44 51
Note: The switching frequency is calculated at maximum output.
In this design example, the minimum primary inductance is
used to achieve a nominal switching frequency of 200kHz at
full load. The 750311458 from Würth Elektronik is chosen
as the fl yback transformer.
Given the turns ratio and primary inductance, a custom-
ized transformer can be designed by magnetic component
manufacturer or a multi-winding transformer such as a
Coiltronics Versa-Pac may be used.
3. Select the output diodes and output capacitor.
The output diode voltage stress V
D
is the summation of
the output voltage and refl ection of input voltage to the
secondary side. The average diode current is the load
current.
VV
V
N
D OUT
IN
=+
The output capacitor should be chosen to minimize the
output voltage ripple while considering the increase in
size and cost of a larger capacitor. The following equation
calculates the output voltage ripple.
ΔV
LI
CV
MAX
PK
OUT
=
2
2
4. Select the snubber circuit to clamp the switch
voltage spike.
A fl yback converter generates a voltage spike during switch
turn-off due to the leakage inductance of the transformer.
In order to clamp the voltage spike below the maximum
rating of the switch, a snubber circuit is used. There are
many types of snubber circuits, for example R-C, R-C-D and
LT3575
17
3575f
APPLICATIONS INFORMATION
Zener clamps. Among them, RCD is widely used. Figure 9
shows the RCD snubber in a fl yback converter.
A typical switch node waveform is shown in Figure 10.
During switch turn-off, the energy stored in the leakage
inductance is transferred to the snubber capacitor, and
eventually dissipated in the snubber resistor.
1
2
2
LI f
VV NV
R
SPKSW
C C OUT
=
(•)
The snubber resistor affects the spike amplitude V
C
and
duration t
SP
, the snubber resistor is adjusted such that
t
SP
is about 150ns. Prolonged t
SP
may cause distortion
to the output voltage sensing.
The previous steps fi nish the fl yback power stage design.
5. Select the feedback resistor for proper output voltage.
Using the resistor Tables 1-4, select the feedback resistor
R
FB
, and program the output voltage to 5V. Adjust the
R
TC
resistor for temperature compensation of the output
voltage. R
REF
is selected as 6.04k.
A small capacitor in parallel with R
REF
lters out the
noise during the voltage spike, however, the capacitor
should limit to 10pF. A large capacitor causes distortion
on voltage sensing.
6. Optimize the compensation network to improve the
transient performance.
The transient performance is optimized by adjusting the
compensation network. For best ripple performance, select
a compensation capacitor not less than 1.5nF, and select
a compensation resistor not greater than 50k.
7. Current limit resistor, soft-start capacitor and UVLO
resistor divider
Use the current limit resistor R
LIM
to lower the current
limit if a compact transformer design is required. Soft-start
capacitor helps during the start-up of the fl yback converter .
Select the UVLO resistor divider for intended input opera-
tion range. These equations are aforementioned.
Figure 9. RCD Snubber in a Flyback Converter Figure 10. Typical Switch Node Waveform
3575 F09
L
S
D
R
C
V
IN
V
C
NV
OUT
t
SP
3575 F10
LT3575
18
3575f
±12V Isolated Flyback Converter
TYPICAL APPLICATIONS
SHDN/UVLO
T
C
SS
SW
VC GND BIAS
LT3575
3575 TA02
R6
28.7k
R5
10k
V
IN
5V
V
OUT
+
5V, 700mA
V
OUT
V
IN
3:1
D1
V
IN
R1
200k
R2
90.9k
C1
10
μF
C5
47
μF
T1
24
μH
2.6
μH
T1: PULSE PA2454NL
D1: PDS835L
D2: PMEG6010
C5: MURATA, GRM32ER71A476K
R4
6.04k
R3
80.6k
C2
10nF
C3
33nF
R7
4.53k
R8
1k
D2
C6
0.22μF
TEST
R
ILIM
R
FB
R
REF
SHDN/UVLO
T
C
SS
SW
VC GND BIAS
LT3575
3575 TA03
R6
59k
R5
10k
V
IN
5V
V
IN
2:1:1
V
IN
R1
200k
R2
90.9k
C1
10
μF
T1
33.2
μH
T1: COILTRONICS VPH2-0083-R
D1, D2: PDS540
D3: PMEG6010
C5, C6: MURATA, GRM32ER71A476K
R4
6.04k
R3
118k
V
OUT1
+
12V, 200mA
V
OUT1
D1
C5
47
μF
8.3μH
V
OUT2
+
V
OUT2
–12V, 200mA
D2
C6
47
μF
8.3μH
C2
10nF
C3
0.1μF
R7
4.99k
R8
1k
D3
C6
0.22
μF
TEST
R
ILIM
R
FB
R
REF
Low Input Voltage 5V Isolated Flyback Converter

MIC28513-2YFL-T5

Mfr. #:
Manufacturer:
Microchip Technology / Micrel
Description:
Switching Voltage Regulators 45V, 4A Synchronous Buck Regulator with HyperSpeed Control
Lifecycle:
New from this manufacturer.
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