MP3312L － 2.7V-5.5V INPUT, 38V OVP, DUAL-CHANNEL WHITE LED DRIVER
MP3312L Rev. 1.0 www.MonolithicPower.com 10
8/11/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
OPERATION
The MP3312L employs a fixed switching
frequency, peak-current-mode control
architecture, and two regulated current sinks to
power the LED array (see Figure 1).
System Start-Up
Pulling EN and PWM high enables the IC while
pulling EN to GND for >2.5ms (or pulling PWM
to GND for >20ms) shuts down the IC.
When enabled, the MP3312L checks the
topology connection first. Also, the MP3312L
checks UVLO and over-temperature protection
(OTP). If all the protections pass, the chip starts
boosting the step-up converter with an internal
soft start.
It is recommended that the enable signal occurs
after the establishment of the input voltage and
PWM dimming signal during the start-up
sequence to avoid large inrush current.
Switching Operation
At the start of each oscillator cycle, the main
low-side FET (M1) is turned on through the
control circuitry. To prevent sub-harmonic
oscillation at a duty cycle greater than 50%, a
stabilizing ramp is added to the output of the
current sense amplifier; the result is fed into the
positive input of the PWM generation
comparator. When this voltage equals the
output voltage of the error amplifier, the main
power FET is turned off. Then the inductor
current flows through the free-wheeling diode,
which forces the inductor current to decrease.
The output voltage of the internal error amplifier
is an amplified signal of the difference between
the reference voltage and the feedback voltage.
The converter chooses the lowest active LEDX
pin voltage automatically to provide a high
enough bus voltage to power all the LED arrays.
If the feedback voltage drops below the
reference, the output of the error amplifier
increases. This results in more current flowing
through the MOSFET, thus increasing the
power delivered to the output. This forms a
closed loop that regulates the output voltage.
Dimming Control
The MP3312L supports analog dimming and 1-
wire digital set dimming mode to regulate the
WLED current.
For analog dimming, apply a PWM signal to
PWM by adjusting the LED current amplitude.
The internal filter is integrated, and the PWM
signal (5k~100kHz range) is supported. The
internal dimming signal duty detection circuit
changes the internal reference linearly to
regulate the current automatically.
In addition, EN supports a 1-wire interface for
current dimming control.
1-Wire Interface
1-wire interface is based on a master-slave
structure, which is designed for digital dimming.
EN is a multipurpose single port that receives
LED brightness data. The rate to detect the bit
ranges from 1.39kit/sec to 50kBit/sec.
The command sent to the chip (slave) contains
24 bits and 9-bit dimming data. Also, an 8-bit
device address and RFA bit are included. The
chip detects the bit in the series and transmits
the LSB first and the MSB last.
Refer to Figure 2 and the description of the
control bits below:
• D0-D8 are the dimming data bits, which
achieve a 9-bit dimming resolution.
• Bit 9 and bit 11-bit 15 are reserved. Set to 0.
• The RFA bit indicates if the master needs to
request acknowledgment or not.
• The device address byte is DA0-DA7. The
device address byte is set to 0x8F.
