X9111
4
FN8159.5
October 13, 2016
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Principles of Operation
Device Description
SERIAL INTERFACE
The X9111 supports the SPI interface hardware conventions. The
device is accessed via the SI input with data clocked-in on the rising
SCK. CS
must be LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since they have three
state outputs. This can help to reduce system pin count.
ARRAY DESCRIPTION
The X9111 is comprised of a resistor array (see Figure 3). The
array contains the equivalent of 1,023 discrete resistive
segments that are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (R
W
) output. Within the
individual array, only one switch may be turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
WIPER COUNTER REGISTER (WCR)
The X9111 contains a Wiper Counter Register (see Table 1 on
page 5) for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs decoded to
select one of 1024 switches along its resistor array. The contents
of the WCR can be altered in one of three ways:
1. It may be written directly by the host via the write Wiper
Counter Register instruction (serial load).
2. It may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register.
3. It is loaded with the contents of its Data Register zero (DR0)
upon power-up.
The Wiper Counter Register is a volatile register, meaning its
contents are lost when the X9111 is powered-down. Although the
register is automatically loaded with the value in R0 upon
power-up, this may be different from the value present at power-
down. Power-up guidelines are recommended to ensure proper
loadings of the R0 value into the WCR.
DATA REGISTERS (DR3 TO DR0)
The potentiometer has four 10-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four Data Registers and the
Wiper Counter Register. All operations changing data in one of
the Data Registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
A DR[9:0] is used to store one of the 1024 wiper positions (0
~1023). See Table 2 on page 5
FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM
SERIAL DATA PATH
FROM INTERFACE
REGISTER 0
SERIAL
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
R
H
R
L
R
W
10 10
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then R
W
= R
L
If WCR = 3FF[HEX] then R
W
= R
H
WIPER
(WCR)
(DR0)
CIRCUITRY
REGISTER 1
(DR1)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
BUS