2
ICS93V857-XXX
0693M—02/19/09
Pin Descriptions
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,12,51,21,11,4
,54,83,43,82
DDVRWPV5.2ylppusrewoP
,52,42,81,8,7,1
84,24,14,13
DNGRWPdnuorG
61DDVARWPV5.2,ylppusrewopgolanA
71DNGARWP.dnuorggolanA
,64,44,93,92,72
3,5,01,02,22
)0:9(TKLCTUO.stuptuoriaplaitnereffidfokcolC"eurT"
,74,34,04,03,62
2,6,9,91,32
)0:9(CKLCTUO.stuptuoriaplaitnereffidfoskcolc"yratnemelpmoC"
41CNI_KLCNItupnikcolcecnerefer"yratnemelpmoC"
31TNI_KLCNItupnikcolcecnerefer"eurT"
33CTUO_BFTUO
tI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF"yratnemelpmoC"
deriwebtsumtuptuosihT.KLCehtsaycneuqerfemasehttasehctiws
.CNI_BFot
23TTUO_BFTUO
sehctiwstI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF""eurT"
otderiwebtsumtuptuosihT.KLCehtsaycneuqerfemasehtta
.TNI_BF
63TNI_BFNI
rofLLPlanretniehtotlangiskcabdeefsedivorp,tupnikcabdeeF"eurT"
.rorreesahpetanimileotTNI_KLChtiwnoitazinorhcnys
53CNI_BFNI
LLPlanretniehtotlangissedivorp,tupnikcabdeeF"yratnemelpmoC"
.rorreesahpetanimileotCNI_KLChtiwnoitazinorhcnysrof
73#DPNItupniSOMCVL.nwoDrewoP
This PLL Clock Buffer is designed for a V
DD
of 2.5V, AV
DD
of 2.5V and differential data input and output levels.
ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV
DD
). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL in ICS93V857-XXX clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]).
ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V857-XXX is characterized for operation from 0°C to 85°C.
