SC121
19
Note that this is a negative quantity, since V
OUT
> V
IN
and
0 < D < 1. For a constant load in steady-state, the inductor
current must satisfy ΔI
L-on
+ ΔI
L-o
= 0. Substituting the two
expressions and solving for D, obtain D = 1 – V
IN
/V
OUT
.
Using this expression, and the positive valued expression
ΔI
L
= ΔI
L-on
for current ripple amplitude, obtain expanded
expression for I
L-max
and I
L-min
.

INOUT
OUT
IN
IN
OUTOUT
max,minL
VV
V
V
L2
T
V
IV
I uu
u
r
Ku
u
From this result, obtain an alternative expression for ΔI
L
.

INOUT
OUT
IN
minLmaxLL
VV
V
V
L
T
III uu '
The inductor selection should consider the n-channel FET
current limit for the expected range of input voltage and
output load current. The largest I
L-avg
will occur at the
expected smallest V
IN
and largest I
OUT
. Determine the
largest expected ΔI
L
. Then for the largest expected I
L-avg
,
ensure that the n-channel FET current limit is not exceed.
That is, for the minimum n-channel FET current limit,
worst case inductor tolerance, highest expected output
current, and lowest expected V
IN
, ensure that
I
L-max
= I
L-avg
+ ΔI
L
/2 < I
LIM(N)
.
Many of these equations include the parameter η, e -
ciency. E ciency varies with V
IN
, I
OUT
, and temperature.
Estimate η using the plots provided in this datasheet, or
from experimental data, at the operating condition of
interest.
Any chosen inductor should have low DCR compared to
the R
DS-ON
of the FET switches to maintain efficiency,
though for DCR << R
DS-ON
, further reduction in DCR will
provide diminishing bene t. The inductor I
SAT
value should
exceed the expected I
L-max
. The inductor self-resonant fre-
quency should exceed 5×f
osc
. Any inductor with these
properties should provide satisfactory performance.
L = 4.7µH should perform well for most applications.
The following table lists the manufacturers of recom-
mended inductor options. The speci cation values shown
are simpli ed approximations or averages of many device
parameters under various test conditions. See manufac-
turers documentation for full performance data.
Manufacturer/
Part #
Value
(H)
DCR
(Ω)
Rated
Current
(mA)
Tolerance
(%)
Dimensions
LxWxH
(mm)
Murata
LQM31PN4R7M00
4.7 0.3 700 20 3.2 x 1.6 x 0.95
Coilcraft
XFL2006-472
4.7 0.7 500 20 2 x 2 x 0.6
Capacitor Selection
Input and output capacitors must be chosen carefully to
ensure that they are of the correct value and rating. The
output capacitor requires a minimum capacitance value
of 10µF at the programmed output voltage to ensure sta-
bility over the full operating range. This must be consid-
ered when choosing small package size capacitors as the
DC bias must be included in their derating to ensure this
required value. For example, a 10µF 0805 capacitor may
provide su cient capacitance at low output voltages but
may be too low at higher output voltages. Therefore, a
higher capacitance value may be required to provide the
minimum of 10µF at these higher output voltages.
Low ESR capacitors such as X5R or X7R type ceramic
capacitors are recommended for input bypassing and
output filtering. Low-ESR tantalum capacitors are not
recommended due to possible reduction in capacitance
seen at the switching frequency of the SC121. Ceramic
capacitors of type Y5V are not recommended as their tem-
perature coe cients make them unsuitable for this appli-
cation. The following table lists recommended capacitors.
For smaller values and smaller packages, it may be neces-
sary to use multiples devices in parallel.
Manufacturer/
Part Number
Value
(F)
Rated Volt-
age (VDC)
Type
Case
Size
Case
Height
(mm)
Murata
GRM21BR60J226ME39B
22 6.3 X5R 0805 1.25
Murata
GRM31CR71A226KE15L
22 10 X7R 1206 1.6
Murata
GRM185R60G475ME15
4.7 4 X5R 0603 0.5
TDK
C2012X5R1A226M
22 10 X5R 0805 0.85
Taiyo Yuden
JMK212BJ226MG-T
22 20 X5R 0805 1.25
Applications Information (continued)
SC121
20
GND
V
IN
C
IN
SC121
FB
ENIN
LX
L
X
R
2
(2
nd
layer)
OUT
GND
7.0mm
5.2mm
C
FB
R
1
V
OUT
C
OUT
Figure 4 — Layout Drawing
PCB Layout Considerations
Poor layout can degrade the performance of the DC-DC
converter and can contribute to EMI problems, ground
bounce, and resistive voltage losses. Poor regulation and
instability can result.
The following simple design rules can be implemented to
ensure good layout:
Place the inductor and  lter capacitors as close
to the device as possible and use short wide
traces between the power components.
Route the output voltage feedback path away
from the inductor and LX node to minimize
noise and magnetic interference.
Maximize ground metal on the component side
to improve the return connection and thermal
dissipation. Separation between the LX node
and GND should be maintained to avoid cou-
pling capacitance between the LX node and the
ground plane.
Use a ground plane with several vias connecting
to the component side ground to further reduce
noise interference on sensitive circuit nodes.
A suggested layout is shown in Figure 4.
Applications Information (continued)
SC121
21
(LASER MARK)
INDICATOR
PIN 1
1
N
2
MIN
aaa
bbb
b
e
L
N
D
A1
A
DIM
MILLIMETERS
NOM
DIMENSIONS
MAXNOM
INCHES
MIN MAX
A
A1
D1
E1
.035
.035.026 .031 0.800.65 0.90
0.90.055
--
1.40
E .079 2.00
--
bxN
A2
(.006) (.152)
.055 .063 1.40 1.60
.075 .083 1.90 2.10
A2
LxN
D
E
E1
D1
NOTES:
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS TERMINALS.
2.
1.
.003
.007
6
.010
.059
.000
.020
0.08
0.25
6
.012 0.18
.024
.002 0.00
0.50
0.30
1.50
0.05
0.60
.004 0.10
0.50 BSC.020 BSC
0.30.012 .016.014 0.35 0.40
aaa
C
SEATING
PLANE
A
bbb C A B
B
e
C
--
Outline Drawing — MLPD-UT-6 1.5x2

SC121ULTRT

Mfr. #:
Manufacturer:
Semtech
Description:
Switching Voltage Regulators LOW VOLTAGE BOOST CONVRTR_PWM
Lifecycle:
New from this manufacturer.
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