MAX1183
(1 to 5), a ferrite bead, or a direct short. Alternatively,
all ground pins could share the same ground plane, if the
ground plane is sufficiently isolated from any noisy, digital
systems ground plane (e.g. downstream output buffer or
DSP ground plane). Route high-speed digital signal
traces away from the sensitive analog traces of either
channel. Make sure to isolate the analog input lines to
each respective converter to minimize channel-to-chan-
nel crosstalk. Keep all signal lines short and free of 90
degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1183 are measured using
the best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 9 depicts the aperture jitter (t
AJ
), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t
AD
) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N-Bits):
SNR
dB[max]
= 6.02 N + 1.76
In reality, there are other noise sources besides quanti-
zation noise (thermal noise, reference noise, clock jitter,
etc.). SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
16 ______________________________________________________________________________________
0°
90°
÷
8
DOWNCONVERTER
MAX2451
INA+
MAX1183
INA-
INB+
INB-
DSP
POST-
PROCESSING
Figure 8. Typical QAM Application, Using the MAX1183
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLK
Figure 9. T/H Aperture Timing
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are backed off by 6.5dB from full scale.
THD
VVVV
V
+++
20
10
2
2
3
2
4
2
5
2
1
log
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 17
GND
REFERENCE
OUTPUT
DRIVERS
CONTROL
T/H
T/H
PIPELINE
ADC
DEC
OUTPUT
DRIVERS
REFOUT
REFN
COM
REFP
REFIN
INA+
INA-
CLK
INB+
INB-
V
DD
DEC
PIPELINE
ADC
OGND
OV
DD
D9A–D0A
OE
D9B–D0B
T/B
PD
SLEEP
MAX1183
10
10
10
10
Functional Diagram
PART
RESOLUTION
(BITS)
SPEED
GRADE
(Msps)
OUTPUT
BUS
MAX1190 10 120 Full-Duplex
MAX1180 10 105 Full-Duplex
MAX1181 10 80 Full-Duplex
MAX1182 10 65 Full-Duplex
MAX1183 10 40 Full-Duplex
MAX1186 10 40 Half-Duplex
MAX1184 10 20 Full-Duplex
MAX1185 10 20 Half-Duplex
MAX1198 8 100 Full-Duplex
MAX1197 8 60 Full-Duplex
MAX1196 8 40 Half-Duplex
MAX1195 8 40 Full-Duplex
Table 2. Pin-Compatible Versions
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
48L,TQFP.EPS
G
1
2
21-0065
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
G
2
2
21-0065
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
Revision History
Pages changed at Rev 1: Title change—all pages,
1-13, 15-18

MAX1183ECM+TD

Mfr. #:
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Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 2Ch 40Msps High Speed ADC
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