8-Bit Serial Input Constant-Current Latched LED Driver
A6277
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
.......................................... 60 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
.............................................. 20 ns
C. Clock Pulse Width, t
w(CK)
............................................... 50 ns
D. Time Between Clock Activation
and Latch Enable, t
su(L)
............................................ 100 ns
E. Latch Enable Pulse Width, t
w(L)
................................... 100 ns
F. Output Enable Pulse Width, t
w(OE)
................................ 4.5 Ms
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
— Max. Clock Transition Time, t
r
or t
f
.............................. 10 Ms
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
CLOCK
SERIAL
DATA IN
LATCH
ENABLE
OUTPUT
ENABLE
OUT
N
Dwg. WP-029-3
50%
SERIAL
DATA OUT.
1
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
SERIAL
DATA OUT.
2
DATA50%
p
t
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-1A
DATA
10%
50%
pHL
t
pLH
t
HIGH = ALL OUTPUTS DISABLED (BLANKED)
f
t
r
t
90%
F
50%
