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HIP4086AABZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
HIP4086, HIP4086A
13
FN4220.11
January 12, 2017
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General PCB Layout Guidelines
The AC performance of the HIP4086/A depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance:
• Place the driver as close as possible to the driven power FETs.
• Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they are usually more effective
than parallel traces.
• Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
• When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10kΩ resistor, is
10x larger than the noise on a 1kΩ resistor.
• Be aware of magnetic fields emanating from motors,
transformers and inductors. Gaps in these magnetic structures
are especially bad for emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
• The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
capacitors must also have the shortest possible conduction
paths. If vias are used, connect several paralleled vias to
reduce the inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits especially on xHO and xLO. If an external gate
resistor is unacceptable, then the layout must be improved to
minimize lead inductance.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
that source the input signals to the HIP4086/A.
• Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (power FETs, electrolytic capacitors,
power resistors, etc.) will have internal parasitic inductance
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
• If you simulate your circuits, consider including parasitic
components especially parasitic lead inductance.
HIP4086, HIP4086A
14
FN4220.11
January 12, 2017
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Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please go to the web to make sure that you have the latest revision.
DATE REVISION CHANGE
January 12, 2017 FN4220.11 The following revisions were made to the DC and AC Electrical Specifications:
-VDD Quiescent Current (HIP4086): updated maximum (T
J
= +25°C) from “4.2” to “5.1”, updated min and
max (T
J
= -40°C to +150°C) from “2.1” to “1.96” and “4.3” to “5.3”, respectively.
-VDD Quiescent Current (HIP4086A): updated max and typical (T
J
= +25°C) from “2.6” to “3.1” and from “2.4”
to “2.8”, updated min and max (T
J
= -40°C to +150°C) from “2.1” to “1.8” and from “2.7” to “3.3”, respectively.
-VDD Operating Current (HIP4086): updated min and max (T
J
= +25°C) from “6.3” to “5.4” and from “10.5”
to “13”, updated min and max (T
J
= -40°C to +150°C) from “5” to “4” and “11” to 13.5”, respectively.
-VDD Operating Current (HIP4086A): updated typical and max (T
J
= +25°C) from “3.6” to “4.0” and from “4.1”
to “4.6”, updated min and max (T
J
= -40°C to +150°C) from “2.8” to “2.7” and from “4.4” to “5.1”, respectively.
-xHB On Quiescent Current (HIP4086): updated maximum (T
J
= +25°C) from “80” to “110”, updated
maximum (T
J
= -40°C to +150°C) from “100” to “140”.
-xHB On Quiescent Current (HIP4086A): updated typical and max (T
J
= +25°C) from “80” to “90” and from
“100” to “115”, updated maximum (T
J
= -40°C to +150°C) from “200” to “225”.
-xHB Off Quiescent Current (HIP4086A): updated typical and max (T
J
= +25°C) from “0.9” to “1.0” and from
“1” to “1.2”, updated maximum (T
J
= -40°C to +150°C) from “1.2” to “1.25”.
-xHB Operating Current (HIP4086A): updated maximum (T
J
= +25°C) from “1” to “1.1”, updated maximum
(T
J
= -40°C to +150°C) from “1.2” to “1.25”.
-xHB, xHS Leakage Current: updated typical (T
J
= +25°C) from “24” to “30”.
-Minimum Undervoltage Threshold: updated min (T
J
= -40°C to +150°C) from “4.9” to “4.8”.
-QPUMP Output Voltage: updated min and max (T
J
= +25°C) from “11.5” to “11” and from “14” to “14.6”,
updated min and max (T
J
= -40°C to +150°C) from “10.5” to “10” and “14.5” to “14.75”, respectively.
-QPUMP Output Current: updated min and max (T
J
= +25°C) from “50” to “40” and from “130” to “160”,
updated maximum (T
J
= -40°C to +150°C) from “140” to “185”.
-Low Level Input Current: updated maximum (T
J
= +25°C) from “-135” to “-155”, updated maximum
(T
J
= -40°C to +150°C) from “-140” to “-165”.
-Low Level Output Voltage: updated maximum (T
J
= -40°C to +150°C) from “200” to “210”.
-Dead Time (RDEL = 100kΩ): updated min and max (T
J
= +25°C) from “3.8” to “3” and from “6” to “7.2”,
updated maximum (T
J
= -40°C to +150°C) from “7” to “8”.
-Dead Time (RDEL = 10kΩ): updated maximum (T
J
= +25°C) from “0.65” to “0.75”, updated maximum
(T
J
= -40°C to +150°C) from “0.7” to “0.8”.
-xLI to xLO turn-off: updated maximum (T
J
= +25°C) from “45” to “55”, updated maximum
(T
J
= -40°C to +150°C) from “65” to “75”.
-xHI
to xHO turn-off: updated maximum (T
J
= +25°C) from “90” to “110”, updated maximum
(T
J
= -40°C to +150°C) from “100” to “135”.
-xLI to xLO turn-on: updated maximum (T
J
= +25°C) from “75” to “82”, updated maximum
(T
J
= -40°C to +150°C) from “90” to “100”.
-xHI
to xHO turn-on: updated maximum (T
J
= +25°C) from “90” to “110”, updated maximum
(T
J
= -40°C to +150°C) from “100” to “158”.
-Rise Time: updated maximum (T
J
= -40°C to +150°C) from “50” to “60”.
-Fall Time: updated maximum (T
J
= -40°C to +150°C) from “25” to “40”.
-DIS
to xLO turn-off: updated maximum (T
J
= -40°C to +150°C) from “90” to “104”.
-DIS
to xHO turn-off: updated maximum (T
J
= +25
°
C) from “90” to “116”, updated maximum
(T
J
= -40°C to +150°C) from “100” to “147”.
-DIS
to xLO turn-on: updated maximum (T
J
= +25
°
C) from “80” to “85”, updated maximum (T
J
= -40°C to
+150°C) from “100” to “120”.
Minor Parameter label changes to use consistent descriptions for related parameters.
Updated from “50µA” to “40µA” in “Charge Pump” and “Selecting the Boot Capacitor Value” on page 11.
March 27, 2015 FN4220.10 Added AN1829, “HIP4086 3-Phase BLDC Motor Drive Demonstration Board, User Guide” bullet to the related
literature section on page 1.
On page 3:
In the Pin Configuration updated typo for Pin 17 Pin Name from “AHC” to “AHO”.
In the Pin Description table:
Updated RDEL and UVLO Description to reference the correct Figures.
RDEL - from “Figure 18” to “Figure 19” and UVLO - from “Figure 19”to “Figure 20”.
Updated typo-AHS pin number from “15” to “18”.
Added “RDEL range10kΩ to 100kΩ” to the “Maximum Recommended Operating Conditions” on page 5.
Updated the About Intersil verbiage.
January 28, 2013 FN4220.9 Corrected following typo in the second paragraph of page 1:
From: (0.5ms to 4.5ms)
To: (0.5µs to 4.5µs)
HIP4086, HIP4086A
15
FN4220.11
January 12, 2017
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Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
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For additional products, see www.intersil.com/en/products.html
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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.
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Reliability reports are also available from our website at www.intersil.com/support
.
September 27, 2012 FN4220.8 Removed evaluation board from “Ordering Information” and “Related Literature” since it is inactive.
June 1, 2011 FN4220.7 Added alternate parameters for HIP4086A in DC Electrical Specifications Table Supply Currents on page 5.
Added to Charge Pump Figures 11 and 12 in Typical Performance Curves “HIP4086 Only”
-Converted to new Intersil datasheet template.
-Changed Title from “80V, 500mA, 3-Phase Driver” to “80V, 500mA, 3-Phase MOSFET Driver”.
-Rewrote description on page 1 by adding HIP4086A and stating the differences between parts.
-Updated “Ordering Information” on page 4 by adding part number HIP4086AABZ and Eval Board. Added MSL
note. Removed obsolete part HIP4086AP.
-Updated “TYPICAL APPLICATION” on page 1.
-Added Figure 2 on page 1.
-Updated “Features” and “Applications” section on page 1.
-Added “” on page 1.
-Updated “Block Diagram” on page 2 by adding color and notes.
-Updated “Thermal Information” and notes on page 5.
-Added “Boldface limits apply..” to common conditions of Electrical Specifications tables. Added Note 9 to MIN
and MAX columns of Electrical Specifications tables.
-Updated all timing diagrams for better clarification on page 7.
-Added “Functional Description”, “Application Information” and “General PCB Layout Guidelines” sections
beginning on page 10.
-Updated Package Outline Drawing M24.3 by removing table listing dimensions and putting dimensions on
drawing. Added Land Pattern.
-Added “Revision History” and “About Intersil” to page 15.
July 26, 2004 FN4220.6 Added Pb-Free parts to “Ordering Information” on page 4.
February 18, 2003 FN4220.5 Revised “Pin Descriptions” on page 3.
Revised “Low Level Input Current” specs on page 6.
May, 1999 FN4220.4 Initial Release.
Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please go to the web to make sure that you have the latest revision. (Continued)
DATE REVISION CHANGE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

HIP4086AABZ

Mfr. #:
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Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 80V 0.5A 3-PHS MOSFE T DRVR
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