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ISL6142/52EVAL1
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P23
10
FIGURE
6A.
DRAIN
HIGH
TO
PWRGD
(INACTIVE)
HIGH
(ISL6142)
FIGURE
6B.
DRAIN HIGH
TO
PWRGD
(INACTIVE) LOW
(ISL6152)
FIGURE 6.
DRAIN TO PWRGD
/PWRGD INACTIVE TIMING
FIGURE 7.
DISABLE TO GA
TE TIMING (ISL6142/52)
FIGURE 8.
FAUL
T T
O G
A
TE TIMING (ISL6142/52)
FIGURE 9.
SENSE TO GA
TE (CURRENT
LIMIT) TIMING
FIGURE 10.
SENSE TO
GA
TE (HARD F
AUL
T) TIMING
FIGURE 1
1.
CUR
RENT LIMIT TO GA
TE TIMING
FIGURE 12.
OUTPUT CURRENT
RISE AND
F
ALL
TIME
T
est Circuit and Timing Diagrams
(Continued)
t
PLHDH
8.0V
1.0V
DRAIN
PWRGD
V
EE
- V
DRAIN
= 0V
V
DRAIN
- V
EE
= 8.0V
V
DH
t
PHLDH
DRAIN
PWRGD
8.0V
1.0V
V
PWRGD
- V
DRAIN
= 0V
V
EE
- V
DRAIN
= 0V
V
DRAIN
- V
EE
= 8.0V
V
DH
DIS
GA
TE
t
PHLDIS
t
PLHDIS
3V
0V
1V
1.50V
2.2V
1V
13.6V
0V
t
PHLF
F
AUL
T
1.0V
1.4V
GA
TE
V
GA
TE
- V
GA
TE
= 0V
SENSE
GA
TE
t
PHLSENSE
~4V (depends on FET threshold)
50mV
13.6V
0V
SENSE
GA
TE
t
PHLHF
V
EE
210mV
13.6V
0V
t
PHLCB
UV
1.0V
1.0V
GA
TE
Over-Current Time-Out
V
SENSE
10%
V
OUT
90%
10%
t
R
t
F
90%
ISL6142, ISL6152
11
T
ypical Performance Curves
FIGURE 13.
SUPPL
Y CURRENT VS. SUPPL
Y VOL
T
AGE (25
o
C)
FIGURE 14.
GA
TE VOL
T
AGE VS SUPPL
Y VOL
T
AGE (25
o
C)
FIGURE 15.
SUPPL
Y CURRENT VS TEMPERA
TURE,
V
DD
= 80V
FIGURE 16.
GA
TE VOL
T
AGE VS TEMPERA
TURE V
DD
= 48V
FIGURE 17.
GA
TE VOL
T
AGE VS TEMPERA
TURE
FIGUR
E 18.
GA
TE PULL-UP CUR
RENT VS TEMPERA
TURE
0
0.
5
1
1.
5
2
2.
5
3
3.
5
4
4.
5
10
20
30
40
50
60
7
0
80
90
100
Suppl
y
Vo
lt
a
g
e
(
VD
D
)
IDD (mA)
0
2
4
6
8
10
12
14
16
10
20
30
40
50
60
70
80
100
Suppl
y
Vol
ta
ge
(VDD
)
Gate Voltage (V)
2.
2
5
2.
3
2.
3
5
2.
4
2.
4
5
2.
5
2.
5
5
2.
6
2.
6
5
2.
7
2.
7
5
-
4
0
-
2
0
0
2
04
06
08
0
1
0
0
T
emperat
u
re
(C
)
IDD (mA)
13.
3
13.
4
13.
5
13.
6
13.
7
13.
8
13.
9
14
-
4
0
-
2
0
0
2
0
4
06
08
0
1
0
0
T
emp
er
at
u
r
e (
C
)
Gate Voltage (V)
13.
4
13.
5
13.
6
13.
7
13.
8
13.
9
14
-
4
0
-
2
0
0
2
04
06
0
8
0
1
0
0
T
emp
eratu
re
(C
)
G
a
te
Vo
ltage (V)
V
DD
= 20V
V
DD
= 80V
41
42
43
44
45
46
47
48
49
50
-
4
0
-
2
0
0
2
04
06
0
8
0
1
0
0
T
emp
er
at
u
r
e
(
C
)
Gate Current (uA)
ISL6142, ISL6152
12
FIGURE 19.
GA
TE PULL-DOWN CURRENT
(UV/OV/TIME-OUT) VS TEMPERA
TURE
FIGURE 20.
HARD F
AUL
T
GA
TE
PULL-DOWN CURRENT
VS
TEMPERA
TURE
FIGURE
21.
OVER-CURRENT
TRIP
VOL
T
AGE
VS
TEMPERA
TURE
FIGURE 22.
PWRGD (ISL6142) VOL VS TEMPERA
TURE
FIGURE
23.
DRAIN
to
PWRGD
/
P
W
R
G
D
T
R
I
P
V
O
LTA
G
E
(
V
PG
)
VS TEMPERA
TURE
FIGURE
24.
PWRGD
(ISL6152)
OUTPUT
IMPEDANCE
VS
TEMPERA
TURE
0
10
20
30
40
50
60
70
80
90
-40
-20
0
20
40
60
80
1
00
T
emp
er
at
u
r
e
(
C
)
Gate Pull Down Current (mA)
0
50
100
150
200
250
300
350
400
450
-40
-2
0
0
2
0
4
0
60
8
0
10
0
T
emp
er
at
u
r
e (
C
)
Gate Pull Down Current (mA)
40
42
44
46
48
50
52
54
-
4
0
-
2
0
0
2
04
06
0
8
0
1
0
0
T
emp
er
at
u
r
e (
C
)
Trip Voltage (mv)
0
0.
2
0.
4
0.
6
0.
8
1
1.
2
1.
4
1.
6
-
4
0
-
2
0
0
2
04
06
0
8
0
1
0
0
T
emp
er
at
u
r
e (
C
)
Output Low Voltage (V)
1mA
5mA
0
0.
5
1
1.
5
2
-
4
0
-
2
0
0
2
0
4
06
08
0
1
0
0
T
emp
er
at
u
r
e (
C
)
Trip Voltage (V)
(1 ma)
6.
1
6.
2
6.
3
6.
4
6.
5
6.
6
6.
7
6.
8
-40
-20
0
20
40
60
80
100
T
emp
er
at
u
r
e (
C
)
Impedance (KOhms)
ISL6142, ISL6152
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P23
ISL6142/52EVAL1
Mfr. #:
Buy ISL6142/52EVAL1
Manufacturer:
Renesas / Intersil
Description:
Power Management IC Development Tools NEG V HOTPLUG CONT BRD W/LOAD CUR MON
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
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Union
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