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MC74HCT138ADG

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 11
1 Publication Order Number:
MC74HCT138A/D
MC74HCT138A
1-of-8 Decoder/
Demultiplexer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT138A is identical in pinout to the LS138. The
HCT138A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The HCT138A decodes a three−bit Address to one−of−eight
active−lot outputs. This device features three Chip Select inputs, two
active−low and one active−high to facilitate the demultiplexing,
cascading, and chip−selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
Features
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
9
10
11
12
13
14
15
3
2
1
CS1
CS2
A0
A1
A2
ACTIVE-LOW
OUTPUTS
ADDRESS
INPUTS
CS3
CHIP-
SELECT
INPUTS
5
4
6
PIN 16 = V
CC
PIN 8 = GND
www.onsemi.com
MARKING DIAGRAMS
SOIC−16
TSSOP−16
1
16
HCT138AG
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
See detailed ordering and shipping information on page 5 o
f
this data sheet.
ORDERING INFORMATION
HCT
138A
ALYWG
G
1
16
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
(Note: Microdot may be in either location)
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A0
CS2
A2
A1
Y7
CS1
CS3
GND
Y3
Y2
Y1
Y0
V
CC
Y5
Y4
Y6
MC74HCT138A
www.onsemi.com
2
Design Criteria Value Units
Internal Gate Count* 30.5 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product .0075 pJ
*Equivalent to a two−input NAND gate.
Inputs Outputs
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H XXXHHHHHHHH
X H X XXXHHHHHHHH
L X X XXXHHHHHHHH
H L L LLLLHHHHHHH
H L L LLHHLHHHHHH
H L L LHLHHLHHHHH
H L L LHHHHHLHHHH
H L L HLLHHHHLHHH
H L L HLHHHHHHLHH
H L L HHLHHHHHHLH
H L L HHHHHHHHHHL
FUNCTION TABLE
H = high level (steady state)
L = low level (steady state)
X = don’t care
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP or SOIC Package)
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HCT138A
www.onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 1) 0 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
−55 to
25_C
≤ 85_C ≤ 125_C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| ≤ 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| ≤ 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 4.0 mA
4.5 3.98 3.84 3.7
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 4.0 mA
4.5 0.26 0.33 0.4
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
5.5 4.0 40 160
mA
DI
CC
Additional Quiescent Supply
Current
V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0 mA
5.5
≥ −55_C 25_C to 125_C
mA
2.9 2.4
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ±10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter
Guaranteed Limit
Unit
−55 to
25_C
≤ 85_C ≤ 125_C
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)
30 38 45 ns
t
PLH
,
t
PHL
Maximum Propagation Delay, CS1 to Output Y
(Figures 2 and 4)
27 34 41 ns
t
PLH
,
t
PHL
Maximum Output Transition Time, CS2 or CS3 to Output Y
(Figures 3 and 4)
30 38 45 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
15 19 22 ns
t
r
, t
f
Maximum Input Rise and Fall Time 500 500 500 ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25°C, V
CC
= 5.0 V
pF
51
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
P1-P3P4-P6P7-P7

MC74HCT138ADG

Mfr. #:
Buy MC74HCT138ADG
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 1OF8 DECODER/ DEMULTIPLER
Lifecycle:
New from this manufacturer.
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