AD8108ASTZ Datasheet AD8109ASTZ, AD8108ASTZ | P19-P21

Data Sheet AD8108/AD8109

Rev. C | Page 19 of 27

output to the disabled state. This is helpful during power-up to

ensure that two parallel outputs are not active at the same time.

After initial power-up, the internal registers in the device

generally has random data, even though the

RESET

signal was

asserted. If parallel programming is used to program one

output, that output is properly programmed, but the rest of the

device has a random program state depending on the internal

programming, it is essential that all outputs be programmed to

a desired state after power-up. This ensures that the programming

matrix is always in a known state. From then on, parallel

programming can be used to modify a single, or more,

output at a time.

In a similar fashion, if both

and

UPDATE

are taken low

after initial power-up, the random power-up data in the shift

the crosspoint from being programmed into an unknown state,

do not apply low logic levels to both

and

UPDATE

after

power is initially applied. Programming the full shift register

one time to a desired state by either serial or parallel programming

after initial power-up eliminates the possibility of programming

the matrix to an unknown state.

To change the programming of an output via parallel

programming,

SER

/PAR and

UPDATE

should be taken high

and

should be taken low. The CLK signal should be in the

high state. The address of the output that is to be programmed

should be put on A0 to A2. The first three data bits (D0 to D2)

should contain the information that identifies the input that is

programmed to the output that is addressed. The fourth data bit

(D3) determines the enabled state of the output. If D3 is low

(output disabled), the data on D0 to D2 does not matter.

After the desired address and data signals have been established,

they can be latched into the shift register by a high to low

transition of the CLK signal. The matrix is not programmed,

however, until the

UPDATE

signal is taken low. Thus, it is

possible to latch in new data for several or all of the outputs first

via successive negative transitions of CLK while

UPDATE

held high, and then have all the new data take effect when

UPDATE

goes low. This technique should be used when

programming the device for the first time after power-up when

using parallel programming.

POWER-ON

RESET

When powering up the AD8108/AD8109, it is usually desirable

to have the outputs come up in the disabled state. When taken

low, the

RESET

pin causes all outputs to be in the disabled state.

However, the

RESET

signal does not reset all registers in the

AD8108/AD8109. This is important when operating in the

parallel programming mode. Please refer to that section for

information about programming internal registers after power-

up. Serial programming programs the entire matrix each time,

so no special considerations apply.

Since the data in the shift register is random after power-up, it

should not be used to program the matrix, or the matrix can

enter unknown states. To prevent this, do not apply logic low

signals to both

and

UPDATE

initially after power-up. The

shift register should first be loaded with the desired data, and

then

UPDATE

can be taken low to program the device.

The

RESET

pin has a 20 kΩ pull-up resistor to DVDD that can

be used to create a simple power-up reset circuit. A capacitor

from

RESET

to ground holds

RESET

low for some time while

the rest of the device stabilizes. The low condition causes all the

outputs to be disabled. The capacitor then charges through the

pull-up resistor to the high state, thus allowing full programming

capability of the device.

GAIN SELECTION

The 8 × 8 crosspoints come in two versions, depending on the

desired gain of the analog circuit paths. The AD8108 device is

unity gain and can be used for analog logic switching and other

applications where unity gain is desired. The AD8108 can also

be used for the input and interior sections of larger crosspoint

arrays where termination of output signals is not usually used.

The AD8108 outputs have very high impedance when their

outputs are disabled.

The AD8109 can be used for devices that is used to drive a

terminated cable with its outputs. This device has a built-in gain

of 2 that eliminates the need for a gain-of-2 buffer to drive a

video line. Because of the presence of the feedback network in

these devices, the disabled output impedance is about 1 kΩ.

If external amplifiers are used to provide a G = 2, the AD8079 is

a fixed gain-of-2 buffer.

AD8108/AD8109 Data Sheet

Rev. C | Page 20 of 27

CREATING LARGER CROSSPOINT ARRAYS

The AD8108/AD8109 are high density building blocks for creating

crosspoint arrays of dimensions larger than 8 × 8. Various features,

such as output disable, chip enable, and gain-of-1 and-2 options,

are useful for creating larger arrays. For very large arrays, they

can be used along with the AD8116, a 16 × 16 video cross-point

device. In addition, systems that require more inputs than

outputs can use the AD8110 and/or the AD8111, which are

(gain-of-1 and gain-of-2) 16 × 8 crosspoint switches.

The first consideration in constructing a larger crosspoint is to

determine the minimum number of devices required. The 8 × 8

architecture of the AD8108/AD8109 contains 64 points, which

is a factor of 16 greater than a 4 × 1 crosspoint. The PC board

area and power consumption savings are readily apparent when

compared to using these smaller devices.

For a nonblocking crosspoint, the number of points required is

the product of the number of inputs multiplied by the number

of outputs. Nonblocking requires that the programming of a

given input to one or more outputs does not restrict the

availability of that input to be a source for any other outputs.

Some nonblocking crosspoint architectures require more than this

minimum as calculated above. Also, there are blocking archi-

tectures that can be constructed with fewer devices than this

minimum. These systems have connectivity available on a statis-

tical basis that is determined when designing the overall system.

The basic concept in constructing larger crosspoint arrays is to

connect inputs in parallel in a horizontal direction and to wire-

OR the outputs together in the vertical direction. The meaning

of horizontal and vertical can best be understood by looking at

a diagram.

An 8 input by 16 output crosspoint array can be constructed as

shown in Figure 48. This configuration parallels two inputs per

channel and does not require paralleling of any outputs. Inputs are

easier to parallel than outputs because there are lower parasitics

involved. For a 16 × 8 crosspoint, the AD8110 (gain of 1) or

AD8111 (gain of 2) device can be used. These devices are

already configured into a 16 × 8 crosspoint in a single device.

8 INPUTS

IN 00–07

16 OUTPUTS

OUT 00–15

ONE

TERMINATION

PER INPUT

AD8108

AD8109

AD8108

AD8109

01068-048

Figure 48. 8 × 16 Crosspoint Array Using Two AD8108 Devices (Unity Gain) or

Two AD8109 Devices (Gain of 2)

Figure 49 illustrates a 16 × 16 crosspoint array, while a 24 × 24

crosspoint is illustrated in Figure 50. The 16 × 16 crosspoint

requires that each input driver drive two inputs in parallel and

each output be wire-OR’ed with one other output. The 24 × 24

crosspoint requires driving three inputs in parallel and having

the outputs wire-OR’ed in groups of three. It is required of the

system programming that only one output of a wired-OR node

be active at a time.

IN 00–07

00–07

08–15

IN 08–15

OUT 00–07 OUT 08–15

TERM

8 × 8

01068-049

Figure 49. 16 × 16 Crosspoint Array Using Four AD8108 Devices or AD8109

Devices

IN 00–07

IN 08

–15

IN 16–23

OUT 16–23OUT 08

–15OUT 00–07

TERM

× 8

8 ×

8 × 8

TERM

8 8

8 8 8

01068-050

Figure 50. 24 × 24 Crosspoint Array Using Nine AD8108 Devices or AD8109

Devices

At some point, the number of outputs that are wire-OR’ed

becomes too great to maintain system performance. This varies

according to which system specifications are most important. For

example, a 64 × 8 crosspoint can be created with eight AD8108/

AD8109 devices. This design has 64 separate inputs and has the

corresponding outputs of each device wire-OR’ed together in

groups of eight.

Data Sheet AD8108/AD8109

Rev. C | Page 21 of 27

Using additional crosspoint devices in the design can lower the

number of outputs that must be wire-OR’ed together. Figure 51

shows a block diagram of a system using eight AD8108 devices

and two AD8109 devices to create a nonblocking, gain-of-2,

64 × 8 crosspoint that restricts the wire-OR’ing at the output to

only four outputs. The rank 1 wire-OR’ed devices are AD8108

devices, which have higher disabled output impedance than the

AD8109.

�

RANK 2

16 × 8 NONBLOCKING

16 BLOCKING

RANK 1

(64:16)

AD8109

AD8108

IN 00

–

OUT 00–07

NONBLOCKING

ADDITIONAL

8 OUTPUTS

(SUBJECT TO

BLOCKING)

IN 08

–15

IN 16–

IN 24–

IN 32–

IN 40

–47

IN 48

–

IN 56–

Ω

01068-051

Figure 51. Nonblocking 64 × 8 Array with Gain of 2 (64 × 16 Blocking)

Additionally, by using the lower four outputs from each of the

two rank 2 AD8109 devices, a blocking 64 × 16 crosspoint array

can be realized. There are, however, some drawbacks to this

technique. The offset voltages of the various cascaded devices

accumulate, and the bandwidth limitations of the devices

compound. In addition, the extra devices consume more

current and take up more board space. Once again, the overall

system design specifications determine how to make the various

tradeoffs.

MULTICHANNEL VIDEO

The excellent video specifications of the AD8108/AD8109 make

them ideal candidates for creating composite video crosspoint

switches. These can be made quite dense by taking advantage of

the high level of integration of the AD8108/AD8109 and the fact

that composite video requires only one crosspoint channel per

system video channel. There are, however, other video formats

that can be routed with the AD8108/AD8109 requiring more

than one crosspoint channel per video channel.

Some systems use twisted-pair wiring to carry video signals.

These systems utilize differential signals and can lower costs

because they use lower cost cables, connectors, and termination

methods. They also have the ability to lower crosstalk and reject

common-mode signals, which can be important for equipment

that operates in noisy environments or where common-mode

voltages are present between transmitting and receiving

equipment.

In such systems, the video signals are differential; there is a

positive and negative (or inverted) version of the signals. These

complementary signals are transmitted onto each of the two

wires of the twisted pair, yielding a first-order zero common-

mode signal. At the receive end, the signals are differentially

received and converted back into a single-ended signal.

When switching these differential signals, two channels are

required in the switching element to handle the two differential

signals that make up the video channel. Thus, one differential

video channel is assigned to a pair of crosspoint channels, both

input and output. For a single AD8108/AD8109, four differential

video channels can be assigned to the eight inputs and eight

outputs. This effectively forms a 4 × 4 differential crosspoint

switch.

Programming such a device requires that inputs and outputs be

programmed in pairs. This information can be deduced by

inspection of the programming format of the AD8108/AD8109

and the requirements of the system.

There are other analog video formats requiring more than one

analog circuit per video channel. One 2-circuit format that is

commonly being used in systems such as satellite TV, digital

cable boxes, and higher quality VCRs is called S-video or Y/C

video. This format carries the brightness (luminance or Y)

portion of the video signal on one channel and the color

(chrominance, chroma, or C) on a second channel.

Since S-video also uses two separate circuits for one video

channel, creating a crosspoint system requires assigning one

video channel to two crosspoint channels, as in the case of a

differential video system. Aside from the nature of the video

format, other aspects of these two systems are the same.

There are yet other video formats using three channels to carry

the video information. Video cameras produce RGB (red, green,

blue) directly from the image sensors. RGB is also the usual

format used by computers internally for graphics. RGB can be

converted to Y, R-Y, B -Y format, sometimes called YUV format.

These 3-circuit video standards are referred to as component

analog video.

The component video standards require three crosspoint

channels per video channel to handle the switching function. In

a fashion similar to the 2-circuit video formats, the inputs and

outputs are assigned in groups of three, and the appropriate

logic programming is performed to route the video signals.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

AD8108ASTZ

Mfr. #:

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Manufacturer:

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Description:

Analog & Digital Crosspoint ICs 325 MHz 8 x 8 Buffered

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AD8108ASTZ

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