OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NCP81278MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P13
NCP81278
www.onsemi.com
4
PIN DESCRIPTION
Pin Name Type Description
1 BST1 Analog Power Bootstrap 1. Provides bootstrap voltage for the high−side gate drive of phase 1. A
0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH1 (pin 20).
2 HG1 Analog Output High−Side Gate 1. Directly connected with the gate of the high−side power MOSFET of
phase 1.
3 EN Logic Input Enable. Logic high enables the device and logic low makes the device in standby mode.
4 PSI Logic Input Power Saving Interface. Logic high enables 2−phase CCM operation, mid level enables
1−phase CCM operation, and logic low enables 1−phase auto CCM/DCM operation.
5 VID Logic Input Voltage ID. Voltage ID input from processor.
6 VIDBUF Analog Output Voltage ID Buffer. VID PWM pulse output from an internal buffer.
7 REFIN Analog Input Reference Input. Reference voltage input for output voltage regulation. The pin is con-
nected to a non−inverting input of internal error amplifier.
8 VREF Analog Output Output Reference Voltage. Precise 2 V reference voltage output. A 10 nF ceramic ca-
pacitor is required from this pin to GND.
9 FS Analog Input Frequency Selection. A resistor from this pin to ground programs switching frequency.
10 FBRTN Analog Input Voltage Feedback Return Input. An inverting input of internal error amplifier.
11 FB Analog Input Feedback. An inverting input of internal error amplifier.
12 COMP/ILMT Analog Output Compensation / ILMT. Output pin of error amplifier. A resistor may be applied between
this pin and GND to program OCP threshold.
13 PGOOD Logic Output Power GOOD. Open−drain output. Provides a logic high valid power good output signal,
indicating the regulator’s output is in regulation window.
14 HG2 Analog Output High−Side Gate 2. Connected with the gate of the high−side power MOSFET in phase 2.
15 BST2 Analog Power Bootstrap 2. Provides bootstrap voltage for the high−side gate drive of phase 2. A
0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH2 (pin 16).
16 PH2 Analog Input Phase Node 2. Connected to interconnection between high−side MOSFET and low−side
MOSFET in phase 2.
17 LG2 Analog Output Low−Side Gate 2. Connected with the gate of the low−side power MOSFET in phase 2.
18 PVCC Analog Power Voltage Supply of Controller and Gate Driver. Power supply input pin of control circuit
and internal gate drivers. A 4.7 mF or larger ceramic capacitor bypasses this input to
ground. This capacitor should be placed as close as possible to this pin.
19 LG1 Analog Output Low−Side Gate 1. Connected with the gate of the low−side power MOSFET in phase 1.
20 PH1 Analog Input Phase Node 1. Connected to interconnection between high−side MOSFET and low−side
MOSFET in phase 1.
21 THERM/GND Analog Ground Thermal Pad and Ground. Common ground of internal control circuits and gate drivers.
Must be connected to the system ground.
NCP81278
www.onsemi.com
5
MAXIMUM RATINGS
Rating Symbol
Value
Unit
Min Max
PH to GND V
PH
−2
−8 (<100 ns)
30 V
Supply Voltage PVCC to GND V
PVCC
−0.3 6.5 V
BST to GND V
BST_GND
−0.3 35 V
BST to PH V
BST_PH
−0.3 6.5 V
HG to PH V
HG
−0.3
−2 (<200 ns)
BST+0.3 V
LG to GND V
LG
−0.3
−2 (<200 ns)
MIN (PVCC+0.3, 6.5) V
FBRTN to GND V
FBRTN
−0.3 0.3 V
Other Pins to GND −0.3 MIN (VCC+0.3, 6.5) V
Human Body Model (HBM) ESD Rating are (Note 1) ESD HBM 2000 V
Machine Model (MM) ESD Rating are (Note 1) ESD MM 200 V
Latch up Current: (Note 2)
All pins, except digital pins
Digital pins
I
LU
−100
−10
100
10
mA
Operating Junction Temperature Range (Notes 3 and 4) T
J
−40 125 °C
Operating Ambient Temperature Range T
A
−40 100 °C
Storage Temperature Range T
STG
−40 150 °C
Thermal Resistance Junction to Top Case (Note 5)
R
Ψ
JC
5 °C/W
Thermal Resistance Junction to Board (Note 5)
R
Ψ
JB
4 °C/W
Thermal Resistance Junction to Ambient (Note 4) R
θ
JA
40 °C/W
Power Dissipation (Note 6) P
D
2.5 W
Moisture Sensitivity Level (Note 7) MSL 1 −
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
4. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM.
5. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM. It is for checking junction temperature using external measurement.
6. The maximum power dissipation (PD) is dependent on input voltage, maximum output current and external components selected. T
ambient
= 25°C, T
junc_max
= 125°C, P
D
= (T
junc_max
−T
_amb
)/Theta JA.
7. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
NCP81278
www.onsemi.com
6
ELECTRICAL CHARACTERISTICS (V
IN
= 12 V, V
PVCC
= 5 V, V
REFIN
= 1.0 V, V
PSI
= 1.8 V, typical values are referenced to
T
A
= T
J
= 25°C, Min and Max values are referenced to T
A
= T
J
= −40°C to 100°C. unless other noted.)
Characteristics Test Conditions Symbol Min Typ Max Units
SUPPLY VOLTAGE
VIN Supply Voltage Range
(Note 8) V
IN
3.6 12 24 V
PVCC Supply Voltage Range (Note 8) V
PCC
4.5 5 5.5 V
PVCC Under−Voltage (UVLO) Threshold PVCC falling V
CCUV−
4.0 4.11 4.2 V
PVCC OK Threshold PVCC rising V
CCOK
4.2 4.31 4.4 V
SUPPLY CURRENT
PVCC Quiescent Current
EN high, no switching
PS0
I
CC
− 4.6 7.5
mA
PS1 − 4.65 7.5
PS2 − 4.59 7.5
PVCC Shutdown Current EN low I
sdPCC
− 27 50
mA
SWITCHING FREQUENCY SETTING
PS0 Switching Frequency Range (Note 8) F
SW
200 800 kHz
FS Voltage
RFS = 39.2 kW
V
FS
2.0 V
VOLTAGE REFERENCE
VREF Reference Voltage I
REF
= 1 mA V
VREF
1.98 2.0 2.02 V
PWM MODULATION
Minimum On Time
(Note 8) T
on_min
50 ns
Minimum Off Time (Note 8) T
off_min
250 ns
VOLTAGE ERROR AMPLIFIER
Open−Loop DC Gain (Note 8) GAIN
EA
80 dB
Unity Gain Bandwidth (Note 8) GBW
EA
20 MHz
Slew Rate (Note 8) SR
COMP
20
V/ms
COMP Voltage Swing
I
COMP
(source) = 2 mA V
maxCOMP
3.1 3.4 − V
I
COMP
(sink) = 2 mA V
minCOMP
− 0.95 1.10 V
FB, REFIN Bias Current V
FB
= V
REFIN
= 1.0 V I
FB
−400 400 nA
Input Offset Voltage V
osEA
= V
REFIN
− V
FB
(Note 8)
T
J
= 25°C
T
J
= −40°C to 100°C
V
osEA
−0.65
−8.5
0.65
8.5
mV
REFIN Discharge Switch ON−Resis-
tance
I
REFIN
(sink) = 2 mA 6.91
W
CURRENT−SENSE AMPLIFIER
Closed−Loop DC Gain
GAIN
CA
−5.0 V/V
−3 dB Gain Bandwidth (Note 8) BW
CA
10 MHz
Input Offset Voltage V
osCS
= V
PH
− V
GND
(Note 8) V
osCS
−500 − 500
mV
ENABLE
EN High Threshold V
highEN
1.5 − − V
EN Low Threshold V
lowEN
− − 0.7 V
EN Hysteresis V
hysEN
350 mV
EN Input Bias Current External 1 K pull−up to 3.3 V I
biasEN
− − 1.0
mA
POWER SAVE INPUT
Connected to PVCC PSH: 2−Phase Auto CCM/DCM Mode V
PVCC
−
0.25
V
High Threshold PS0: 2−Phase CCM Mode V
highPSI
1.5 V
Mid Voltage level PS1: 1−Phase CCM Mode V
midPSI
0.6 1.2 V
8. Guaranteed by design, not tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P13

NCP81278MNTXG

Mfr. #:
Buy NCP81278MNTXG
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 4.5 TO 24V 2 PHASE CON
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet