1. General description
The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the
40103 of the 4000B series. The 74HC40103 is specified in compliance with JEDEC
standard no. 7A.
The 74HC40103 consists of an 8-bit synchronous down counter with a single output which
is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary
counter and has control inputs for enabling or disabling the clock (CP), for clearing the
counter to its maximum count and for presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count output (TC) are active-LOW
logic.
In normal operation, the counter is decremented by one count on each positive-going
transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is
HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is
LOW, and remains LOW for one full clock period.
When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7)
is clocked into the counter on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam
input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE,
TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is asynchronously cleared to its
maximum count (decimal 255) regardless of the state of any other input.
If all control inputs except TE are HIGH at the time of zero count, the counters will jump to
the maximum count, giving a counting sequence of 256 clock pulses long.
The 74HC40103 may be cascaded using the TE input and the TC output, in either a
synchronous or ripple mode.
74HC40103
8-bit synchronous binary down counter
Rev. 03 — 12 November 2004 Product data sheet
