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CSPT857CNLG8

P1-P3P4-P6P7-P9P10-P12P13-P15
4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
VDDQ
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
32
31
30
29
1
V
DDQ
VDDQ
GND
25
26
27
28
GND
Y
5
Y5
GND
Y
0
Y0
Y1
Y1
GND
Y
2
Y2
CLK
CLK
AV
DD
Y3
Y3
VDDQ
Y4
Y6
Y6
GND
Y
7
Y7
PWRDWN
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
Y
8
Y8
VDDQ
Y9
Y9
GND
GND
GND
Y4
GND
V
DDQ
VDDQ
VDDQ
AGND
PIN CONFIGURATIONS
TSSOP
TOP VIEW
VFQFPN
TOP VIEW
GND
Y
2
Y2
VDDQ
CLK
CLK
V
DDQ
AVDD
AGND
GND
Y
3
Y
3
V
D
D
Q
Y
4
Y
4
Y
9
Y
9
V
D
D
Q
Y
8
Y
8
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
V
DDQ
VDDQ
FBOUT
FBOUT
Y
1
Y
1
V
D
D
Q
Y
0
Y
0
Y
5
Y
5
V
D
D
Q
Y
6
Y
6
GND
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
30
29
28
27
26
25
24
23
22
21
31323334353637383940
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Max Unit
VDDQ, AVDD Supply Voltage Range –0.5 to +3.6 V
VI
(2)
Input Voltage Range –0.5 to VDDQ + 0.5 V
VO
(2)
Voltage range applied to any –0.5 to VDDQ + 0.5 V
output in the high or low state
IIK Input Clamp Current –50 mA
(VI <0)
IOK Output Clamp Current ±50 mA
(VO <0 or
VO > VDDQ)
IO Continuous Output Current ±50 mA
(VO =0 to VDDQ)
VDDQ or GND Continuous Current ±100 mA
TSTG Storage Temperature Range – 65 to +150 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
CAPACITANCE
(1)
Parameter Description Min. Typ. Max. Unit
CIN Input Capacitance 2.5 — 3.5 pF
VI = VDDQ or GND
CI(Δ) Delta Input Capacitance -0.25 — 0.25 pF
VI = VDDQ or GND
CL Load Capacitance — 14 — pF
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
5
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (TSSOP/TVSOP)
Pin Name Pin Number Description
AGND 17 Ground for analog supply
AVDD 16 Analog supply
CLK, CLK 13, 14 Differential clock input
FBIN, FBIN 35, 36 Feedback differential clock input
FBOUT, FBOUT 32, 33 Feedback differential clock output
GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 Ground
PWRDWN 37 Output enable for Y and Y
VDDQ 4, 11, 12, 15, 21, 28, 34, 38, 45 I/O supply
Y[0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 Buffered output of input clock, CLK
Y[0:9] 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 Buffered output of input clock, CLK
PIN DESCRIPTION (VFBGA)
Pin Name Pin Number Description
AGND H1 Ground for analog supply
AVDD G2 Analog supply
CLK, CLK F1, F2 Differential clock input
FBIN, FBIN F5, F6 Feedback differential clock input
FBOUT, FBOUT H6, G5 Feedback differential clock output
GND A3, A4, C1, C2, C5, C6, H2, H5, K3, K4 Ground
PWRDWN E6 Output enable for Y and Y
VDDQ B3, B4, E1, E2, E5, G1, G6, J3, J4 I/O supply
Y[0:9] A1, A6, B2, B5, D1, D6, J2, J5, K1, K6 Buffered output of input clock, CLK
Y[0:9] A2, A5, B1, B6, D2, D5, J1, J6, K2, K5 Buffered output of input clock, CLK
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
AVDD Supply Voltage VDDQ – 0.12 VDDQ 2.7 V
V
DDQ I/O Supply Voltage PC1600-PC2700 2.3 2.5 2.7 V
PC3200 2.5 2.6 2.7
T
A Operating Free-Air Temperature -40 ⎯ +85 °C
PIN DESCRIPTION (MLF)
Pin Name Pin Number Description
AGND 9 Ground for analog supply
AVDD 8 Analog supply
CLK, CLK 5, 6 Differential clock input
FBIN, FBIN 25, 26 Feedback differential clock input
FBOUT, FBOUT 21, 22 Feedback differential clock output
GND 1, 10 Ground
PWRDWN 27 Output enable for Y and Y
VDDQ 4, 7, 13, 18, 23, 24, 28, 33, 38 I/O supply
Y[0:9] 3, 12, 14, 17, 19, 29, 32, 34, 37, 39 Buffered output of input clock, CLK
Y[0:9] 2, 11, 15, 16, 20, 30, 31, 35, 36, 40 Buffered output of input clock, CLK
6
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. AVDD nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD nominal is 2.6V for PC3200.
3. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs
= tristate.
FUNCTION TABLE
(1)
INPUTS OUTPUTS
AVDD PWRDWN CLK CLK Y Y FBOUT FBOUT PLL
GND H L H L H L H Bypassed/OFF
GND H H L H L H L Bypassed/OFF
X L L H Z Z Z Z OFF
X L H L Z Z Z Z OFF
Nominal
(2)
HLHLHL H ON
Nominal
(2)
HHLHLH L ON
Nominal
(2,3)
X <20MHz <20MHz Z Z Z Z OFF
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC1600 -
PC2700
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C
Symbol Parameter Conditions Min. Typ. Max. Unit
VIK Input Clamp Voltage (All Inputs) VDDQ = 2.3V, II = -18mA ⎯⎯– 1.2 V
VIL (dc) Static Input LOW Voltage PWRDWN – 0.3 ⎯ 0.7 V
VIH (dc) Static Input HIGH Voltage PWRDWN 1.7 ⎯ VDDQ + 0.3
VIL (ac) Dynamic Input LOW Voltage CLK, CLK, FBIN, FBIN ⎯⎯0.7 V
VIH (ac) Dynamic Input HIGH Voltage CLK, CLK, FBIN, FBIN 1.7 VDDQ
VOL Output LOW Voltage AVDD/VDDQ = Min., IOL = 100μA ⎯ 0.1 V
AVDD/VDDQ = Min., IOL = 12mA ⎯ 0.6
VOH Output HIGH Voltage AVDD/VDDQ = Min., IOH = -100μAVDDQ – 0.1 V
AVDD/VDDQ = Min., IOH = -12mA 1.7
VIX Input Differential Cross Voltage VDDQ/2 – 0.2 VDDQ/2 + 0.2 V
VID(DC)
(1)
DC Input Differential Voltage 0.36 VDDQ + 0.6 V
VID(AC)
(1)
AC Input Differential Voltage 0.7 VDDQ + 0.6 V
IIN Input Current VDDQ = 2.7V, VI = 0V to 2.7V ±10 μA
IDDPD Power-Down Current on VDDQ and AVDD AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L ⎯ 100 200 μA
IDDQ Dynamic Power Supply Current on VDDQ AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF ⎯ 320 360 mA
AVDD/VDDQ = Max., CLK = 170MHz, 120Ω/14pF ⎯ 250 300
IADD Dynamic Power Supply Current on AVDD AVDD/VDDQ = Max., CLK = 170MHz ⎯ 12 mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
P1-P3P4-P6P7-P9P10-P12P13-P15

CSPT857CNLG8

Mfr. #:
Buy CSPT857CNLG8
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2.5V DDR CLK DRIVER
Lifecycle:
New from this manufacturer.
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