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LTC4235IUFD-2#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC4235
16
4235f
For more information www.linear.com/LTC4235
applicaTions inForMaTion
REG Pin Bypassing
The LTC4235 has an internally regulated supply near
SENSE
+
for internal bias of the current sense amplifier. It
is not intended for use as a supply or bias pin for external
circuitry. A 0.1µF capacitor should be connected between
the REG and SENSE
+
pins. This capacitor should be located
very near to the device and close to the REG pin for the
best performance.
REG and IMON Start-Up
The start-up current of the current sense amplifier when
the LTC4235 is powered on consists of two parts: the
first is the current necessary to charge the REG bypass
capacitor, which is nominally 0.1µF. Since the REG voltage
charges to approximately 4.1V below the SENSE
+
voltage,
this can require a significant amount of start-up current.
The second source is the output current that flows into
R
OUT
, which upon start-up may temporarily drive the
IMON output high for less than 2ms. This is a temporary
condition which will cease when the sense amplifier settles
into normal closed-loop operation.
CPO and DGATE Start-Up
The CPO and DGATE pin voltages are initially pulled up
to a diode below the IN pin when
first powered up. CPO
starts ramping up 7µs after INTV
CC
clears its undervolt-
age lockout level. Another 40µs later, DGATE also starts
ramping
up with CPO. The CPO ramp rate is determined
by the CPO pull-up current into the combined CPO and
DGATE pin capacitances. An internal clamp limits the CPO
pin voltage to 12V above the IN pin, while the final DGATE
pin voltage is determined by the gate drive amplifier. An
internal 12V clamp limits the DGATE pin voltage above IN.
CPO Capacitor Selection
The recommended value of the capacitor between the CPO
and IN pins is approximately 10× the input capacitance
C
ISS
of the ideal diode MOSFET. A larger capacitor takes
a correspondingly longer time to charge up by the internal
charge pump. A smaller capacitor suffers more voltage
drop during a fast gate turn-on event as it shares charge
with the MOSFET gate capacitance.
MOSFET Selection
The LTC4235 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance R
DS(ON)
, the maximum drain-source voltage
BV
DSS
and the threshold voltage.
The gate drive for the ideal diode and Hot Swap MOSFET
is guaranteed to
be greater than 10V and is limited to 14V.
An
external Zener diode can be used to clamp the potential
from the MOSFET’s gate to source if the rated breakdown
voltage is less than 14V.
The maximum allowable drain-source voltage BV
DSS
must be higher than the supply voltage including supply
transients as the full supply voltage can appear across the
MOSFET. If an input or output is connected to ground, the
full supply voltage will appear across the MOSFET. The
R
DS(ON)
should be small enough to conduct the maximum
load current, and also stay within the MOSFET’s power
rating.
Supply Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current during input or output
short-circuit events can cause transients that exceed the
24V absolute maximum ratings of the IN and OUT pins.
To minimize such spikes, use wider traces or heavier
trace plating to reduce the power trace inductance. Also,
bypass locally with a 10µF electrolytic and 0.1µF ceramic,
or alternatively clamp the input with a transient voltage
suppressor (Z1, Z2). A 100Ω, 0.1µF snubber damps the
response and eliminates ringing (See Figure10).
Design Example
As a design
example for selecting components, consider a
12V system with a 7A maximum load current for the two
supplies (see Figure1).
First, select the appropriate value of the current sense
resistor R
S
for the 12V supply. Calculate the sense resistor
value based on the maximum load current I
LOAD(MAX)
and
LTC4235
17
4235f
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the lower limit for the current limit sense voltage threshold
∆V
SENSE(TH)(MIN)
.
R
S
=
Δ
V
SENSE(TH)(MIN)
I
LOAD(MAX)
=
22.5mV
7A
= 3.2mΩ
Choose a 3mΩ sense resistor with a 1% tolerance.
Next, calculate the R
DS(ON)
of the ideal diode MOSFET to
achieve the desired forward drop at maximum load. Assum-
ing a
forward drop,
∆V
FWD
of 30mV across the MOSFET:
R
DS(ON)
≤
Δ
V
FWD
I
LOAD(MAX)
=
30mV
7A
= 4.2mΩ
The SiR158DP offers a good choice with a maximum
R
DS(ON)
of 1.8mΩ at V
GS
= 10V. The input capacitance
C
ISS
of the SiR158DP is about 4980pF. Slightly exceeding
the 10× recommendation, a 0.1µF capacitor is selected
for C2 and C3 at the CPO pins.
Next, verify that the thermal ratings of the selected Hot
Swap MOSFET are not exceeded during power-up or an
overcurrent fault.
Assuming the MOSFET dissipates power due to inrush
current charging the load capacitor C
L
at power-up, the
energy dissipated in the MOSFET is the same as the energy
stored in the load capacitor, and is given by:
E
CL
=
1
2
• C
L
• V
IN
2
For C
L
= 680µF, the time it takes to charge up C
L
is cal-
culated as:
t
CHARGE
=
C
L
• V
IN
I
INRUSH
=
680µF •12V
1A
= 8ms
The inrush current is set to 1A by adding capacitance C
HG
at the gate of the Hot Swap MOSFET.
C
HG
=
C
L
• I
HGATE(UP)
I
INRUSH
=
680µF • 10µA
1A
= 6.8nF
Choose a practical value of 10nF for C
HG
.
The average power dissipated in the MOSFET is calculated as:
P
AVG
=
E
CL
t
CHARGE
=
1
2
•
680µF • 12V
( )
2
8ms
= 6W
The MOSFET selected must be able to tolerate 6W for 8ms
during power-up. The SOA curves of the SiR158DP provide
45W (1.5A at 30V) for 100ms. This is sufficient to satisfy
the requirement. The increase in junction temperature due
to the power dissipated in the MOSFET is ∆T=P
AVG
•Zth
JC
where Zth
JC
is the junction-to-case thermal impedance.
Under this condition, the SiR158DP data sheet indicates
that the junction temperature will increase by 3°C using
Zth
JC
= 0.5°C/W (single pulse).
Next, the power dissipated in the MOSFET during an
overcurrent fault must be safely limited. The fault timer
capacitor (C
FT
) is used to prevent power dissipation in
the MOSFET from exceeding the SOA rating during active
current limit. A good way to determine a suitable value
for C
FT
is to superimpose the foldback current limit profile
shown in the Typical Performance Characteristics on the
MOSFET data sheet’s SOA curves.
For the SiR158DP MOSFET, this exercise yields the plot
in Figure6.
1ms
10ms
100ms
1s
10s
DC
BVDSS LIMITED
I
D
LIMITED
I
DM
LIMITED
LIMITED BY R
DS(ON)
*
MOSFET POWER
DISSIPATION CURVE
RESULTING FROM
FOLDBACK ACTIVE
CURRENT LIMIT
V
DS
– DRAIN-TO-SOURCE VOLTAGE (V)
I
D
– DRAIN CURRENT (A)
4235 F06
100
10
1
0.1
0.01
0.01 10 10010.1
* V
GS
> MINIMUM V
GS
AT WHICH R
DS(ON)
IS SPECIFIED
Figure6. SiR158DP SOA with Design Example
MOSFET Power Dissipation Superimposed
LTC4235
18
4235f
For more information www.linear.com/LTC4235
applicaTions inForMaTion
As can be seen, the LTC4235’s foldback current limit profile
roughly coincides with the 100ms SOA contour. Since
this SOA plot is for an ambient temperature of 25°C only,
a maximum fault timer period of much less than 100ms
should be considered, such as 10ms or less. Selecting a
0.1µF ±10% value for C
FT
yields a maximum fault timer
period of 1.75ms which should be small enough to protect
the MOSFET during any overcurrent fault scenario.
Next, select the values for the resistive divider at the ON
pin that defines the undervoltage threshold of 9.7V for the
12V supply at SENSE
+
. Since the leakage current for the
ON pin can be as high as ±1µA, the total resistance in the
divider should be low enough to minimize the resulting
offset error. Calculate the bottom resistor R1 based on
the following equation to obtain less than ±0.2% error
due to leakage current.
R1=
V
ON(TH)
I
IN(LEAK)
⎛
⎝
⎜
⎞
⎠
⎟
• 0.2% =
1.235V
1µA
⎛
⎝
⎜
⎞
⎠
⎟
• 0.2% = 2.4k
Choose R1 to be 2k to achieve less than ±0.2% error and
calculating R2 yields:
R2 =
V
IN(UV)
V
ON(TH)
– 1
⎛
⎝
⎜
⎞
⎠
⎟
• R1
R2 =
9.7V
1.235V
– 1
⎛
⎝
⎜
⎞
⎠
⎟
• 2k = 13.7k
The final components to consider are a 0.1µF bypass (C1)
at the INTV
CC
pin and a 0.1µF capacitor (C4) connected
between the REG and SENSE
+
pins.
•
C4
D G
D S
D S
D S
S D
S D
S D
G D
S D
S D
S D
G D
•••
•
•
•
•
•
•
•• •
•
•••
Z2
Z1
R
S
M
H
PowerPAK SO-8
M
D1
PowerPAK SO-8
M
D2
PowerPAK SO-8
WIN1
VIA TO IN1
CURRENT FLOW
TO LOAD
C3
4235 F08
20 19 18 17
7
1
2
3
4
5
6
16
15
14
13
12
11
8 9 10
LTC4235UFD
C2
R
H
C1
OUT
W
WIN2
CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMPERE
ON 1oz Cu FOIL
VIA TO C2 (CPO1)
VIA TO DGATE2
VIA TO SENSE
+
VIA TO GND PLANE
VIA TO GND PLANE
VIA TO GND PLANE
VIA TO DGATE1
VIA TO C4 (REG)
Figure7. Recommended PCB Layout for Power MOSFETs and Sense Resistor
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LTC4235IUFD-2#TRPBF

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Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Dual 12V Ideal Diode-OR and Single Hot Swap Controller with Current Monitor, Retry Version
Lifecycle:
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