10
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3207E: 469
ICL3217E: 488
PROCESS:
Si Gate CMOS
FIGURE 12. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE
Typical Performance Curves V
CC
= 3.3V, T
A
= 25°C (Continued)
50
55
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20kbps
250kbps
120kbps
1 TRANSMITTER SWITCHING
SUPPLY CURRENT (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5
NO LOAD
ALL OUTPUTS STATIC
ICL3207E, ICL3217E
11
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com
.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
August 21, 2015 FN4914.6 Updated Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M24.3 to the latest revision updates are as follows:
-Revision 0 to Revision 1, Removed µ symbol which is overlapping the alpha symbol in the diagram.
-Revision 1 to Revision 2, Updated to new POD standard by removing table listing dimensions and putting
dimensions on drawing. Added Land Pattern.
ICL3207E, ICL3217E
12
ICL3207E, ICL3217E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm
(0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H
µ
0.25(0.010) BM M
0.25
0.010
GAUGE
PLANE
A2
M24.209 (JEDEC MO-150-AG ISSUE B)
24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.312 0.334 7.90 8.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N24 247
0
o
8
o
0
o
8
o
-
Rev. 1 3/95

ICL3217EIB

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC TXRX RS-232 3-5.5V ESD 24SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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