2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 11 Rev A 3/12/15
5T93GL04 DATA SHEET
FSEL Operation for When Opposite Clock Dies
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When
this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after a number
of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied LOW for systems that use only one input. If this is not possible, the user must guarantee that the
unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
Selection of Input While Protecting Against When Opposite Clock Dies
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with
the input clock selected by the SEL pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will
be driven LOW and will restart with the input clock selected by the SEL pin.
A2 -A2
A1 -A1
FSEL
VTHI
VIH
VIL
+VDIF
VDIF=0
-V
DIF
VTHI
VIH
VIL
+VDIF
VDIF=0
-V
DIF
+VDIF
VDIF=0
-V
DIF
Qn - Qn
SEL