74F652SCX Datasheet 74F652SC, 74F652SPC, 74F652SCX | P1-P3

March 1988

Revised January 2004

74F652 Transceivers/Registers

74F652

Transceivers/Registers

General Description

These devices consist of bus transceiver circuits with

D-type flip-flops, and control circuitry arranged for multi-

plexed transmission of data directly from the input bus or

from internal registers. Data on the A or B bus will be

clocked into the registers as the appropriate clock pin goes

to HIGH logic level. Output Enable pins (OEAB, OEBA

) are

provided to control the transceiver function.

Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ 74F652 non-inverting data path

Ordering Code:

Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F652SC

(Note 1)

M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74F652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

74F652

Unit Loading/Fan Out

Function Table

H = HIGH Voltage Level X = Immaterial

L = LOW Voltage Level

= LOW-to-HIGH Clock Transition

Note 2: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,

i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

Pin Names Description

U.L.

Input I

HIGH/LOW

Output I

–A

, B

–B

A and B Inputs/ 1.0/1.0 20 µA/−0.6 mA

3-STATE Outputs 600/106.6 (80)

−12 mA/64 mA (48 mA)

CPAB, CPBA Clock Inputs 1.0/1.0 20

µA/−0.6 mA

SAB, SBA Select Inputs 1.0/1.0 20

µA/−0.6 mA

OEAB, OEBA

Output Enable Inputs 1.0/1.0 20 µA/−0.6 mA

Inputs Inputs/Outputs (Note 2)

Operating Mode

OEAB OEBA

CPAB CPBA SAB SBA

thru A

thru B

L H H or L H or L X X Input Input Isolation

X X Store A and B Data

H or L X X Input Not Specified Store A, Hold B

X X Input Output Store A in Both Registers

LXH or L

X X Not Specified Input Hold A, Store B

X X Output Input Store B in Both Registers

L L X X X L Output Input Real-Time B Data to A Bus

L L X H or L X H Store B Data to A Bus

H H X X L X Input Output Real-Time A Data to B Bus

H H H or L X H X Stored A Data to B Bus

H L H or L H or L H H Output Output Stored A Data to B Bus and

Stored B Data to A Bus

3 www.fairchildsemi.com

74F652

Functional Description

In the transceiver mode, data present at the HIGH imped-

ance port may be stored in either the A or B register or

both.

The select (SAB, SBA) controls can multiplex stored and

real-time.

The examples in Figure 1 demonstrate the four fundamen-

tal bus-management functions that can be performed with

the Octal bus transceivers and receivers.

Data on the A or B data bus, or both can be stored in the

internal D flip-flop by LOW-to-HIGH transitions at the

appropriate Clock Inputs (CPAB, CPBA) regardless of the

Select or Output Enable Inputs. When SAB and SBA are in

the real time transfer mode, it is also possible to store data

without using the internal D flip-flops by simultaneously

enabling OEAB and OEBA. In this configuration each Out-

put reinforces its Input. Thus when all other data sources to

the two sets of bus lines are in a HIGH impedance state,

each set of bus lines will remain at its last state.

FIGURE 1.

Note A: Real-Time Note B: Real-Time

Transfer Bus B to Bus A Transfer Bus A to Bus B

OEAB OEBA

CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA

LLXXXL HHXXLX

Note C: Storage Note D: Transfer Storage

Data to A or B

OEAB OEBA

CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA

X X X H L H or L H or L H X

LXX

P1-P3 P4-P6 P7-P8

74F652SCX

Mfr. #:

Buy 74F652SCX

Manufacturer:

ON Semiconductor

Description:

IC TXRX NON-INVERT 5.5V 24SOIC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

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74F652SCX

74F652SCX

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