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LTM8047IY

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
LTM8047
10
8047fc
For more information www.linear.com/LTM8047
APPLICATIONS INFORMATION
BIAS Pin Considerations
The BIAS pin is the output of an internal linear regulator
that powers the LTM8047’s internal circuitry. It is set to
3V and must be decoupled with a low ESR capacitor of at
least 4.7μF. The LTM8047 will run properly without apply
-
ing a voltage to this pin, but will operate more efficiently
and dissipate less power if a voltage greater than 3.1V is
applied. At low V
IN
, the LTM8047 will be able to deliver
more output current if BIAS is 3.1V or greater. Up to 40V
may be applied to this pin, but a high BIAS voltage will
cause excessive power dissipation in the internal circuitry.
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the V
IN
pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the V
IN
pin, either powered from
a separate voltage source or left running from the internal
regulator. This has the added advantage of keeping the
physical size of the BIAS capacitor small. Do not allow
BIAS to rise above V
IN
.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at start-up. The built-in soft-start circuit
significantly reduces the start-up current spike and output
voltage overshoot by applying a capacitor from SS to GND.
When the LTM8047 is enabled, whether from V
IN
reaching
a sufficiently high voltage or RUN being pulled high, the
LTM8047 will source approximately 10µA out of the SS
pin. As this current gradually charges the capacitor from
SS to GND, the LTM8047 will correspondingly increase
the power delivered to the output, allowing for a graceful
turn-on ramp.
Isolation and Working Voltage
The LTM8047 isolation is 100% hi-pot tested by tying
all of the primary pins together, all of the secondary pins
together and subjecting the two resultant circuits to a dif
-
ferential of 725VDC for one second and then –725VDC for
one second. This establishes the isolation voltage rating
of the L
TM8047 component, and is most often used to
satisfy component safety specifications issued by agencies
such as UL, TUV, CSA and others.
The isolation rating of the LTM8047 is not the same as
the working or operational voltage that the application
will experience. This is subject to the application’s power
source, operating conditions, the industry where the end
product is used and other factors that dictate design re
-
quirements such as the gap between copper planes, traces
and component pins on the printed circuit board, as well
as the type of connector that may be used. To maximize
the allowable working voltage, the LTM8047 has a row of
solder balls removed to facilitate the printed circuit board
design. The ball to ball pitch is 1.27mm, and the typical ball
diameter is 0.78mm. Accounting for the missing row and
the ball diameter, the printed circuit board may be designed
for a metal-to-metal separation of up to 1.76mm. This may
have to be reduced somewhat to allow for tolerances in
solder mask or other printed circuit board design rules.
To reiterate, the manufacturer’s isolation voltage rating
and the required operational voltage are often different
numbers. In the case of the LTM8047, the isolation voltage
rating is established by 100% hi-pot testing. The working
or operational voltage is a function of the end product
and its system level specifications. The actual required
operational voltage is often smaller than the manufacturer’s
isolation rating.
For those situations where information about the spacing
of LTM8047 internal circuitry is required, the minimum
metal to metal separation of the primary and secondary
is 0.44mm.
ADJ and Line Regulation
For V
OUT
greater than 8V, a capacitor connected from ADJ
to GND improves line regulation. Figure 1 shows the ef-
fect of three capacitance values applied to ADJ for a load
of 15mA. No capacitance has poor line regulation, while
12pF has improved line regulation. As the capacitance
increases, the line regulation begins to degrade again, but
in the opposite direction as having too little capacitance.
Furthermore,
too
much capacitance from ADJ to GND may
increase the minimum load required for proper regulation.
LTM8047
11
8047fc
For more information www.linear.com/LTM8047
APPLICATIONS INFORMATION
A few rules to keep in mind are:
1. Place the R
ADJ
resistor as close as possible to its re-
spective pin.
2.
Place the C
IN
capacitor as close as possible to the V
IN
and GND connections of the LTM8047.
3. Place the C
OUT
capacitor as close as possible to V
OUT
and V
OUT
–
.
4. Place the C
IN
and C
OUT
capacitors such that their
ground current flow directly adjacent or underneath
the LTM8047.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8047.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 2. The LTM8047 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
Figure 2. Layout Showing Suggested External Components,
Planes and Thermal Vias
8047 F02
BIAS
RUN
GND
ADJ
LTM8047
SS
C
OUT
V
OUT
–
V
IN
V
OUT
C
IN
THERMAL/INTERCONNECT VIAS
V
OUT
to V
OUT
–
Reverse Voltage
The LTM8047 cannot tolerate a reverse voltage from V
OUT
to V
OUT
–
during operation. If V
OUT
–
raises above V
OUT
dur-
ing operation, the LTM8047 may be damaged. To protect
against this condition, a low for
ward drop power Schottky
diode has been integrated into the LTM8047, anti-parallel
to V
OUT
/V
OUT
–
. This can protect the output against many
reverse voltage faults. Reverse voltage faults can be both
steady state and transient. An example of a steady state
voltage reversal is accidentally misconnecting a powered
LTM8047 to a negative voltage source. An example of
transient voltage reversals is a momentary connection to
a negative voltage. It is also possible to achieve a V
OUT
reversal if the load is short-circuited through a long cable.
The inductance of the long cable forms an LC tank circuit
with the V
OUT
capacitance, which drives V
OUT
negative.
Avoid these conditions.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8047. The LTM8047 is neverthe
-
less a switching power supply, and care must be taken to
minimize electrical noise to ensure proper operation. Even
with the high level of integration, you may fail to achieve
specified operation with a haphazard or poor layout. See
Figure 2 for a suggested layout. Ensure that the grounding
and heat sinking are acceptable.
Figure 1. For higher output voltages, the LTM8047 requires some
capacitance from ADJ to GND for proper line regulation
LTM8047 Line Regulation
12VOUT, 15mA Output Current
V
IN
(V)
V
OUT
(V)
12.50
11.75
12.25
10.75
11.25
12.00
11.50
11.00
8047 F01
0 10
25
20155
NO CAP
12pF
18pF
LTM8047
12
8047fc
For more information www.linear.com/LTM8047
APPLICATIONS INFORMATION
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
The printed circuit board construction has an impact on
the isolation performance of the end product. For example,
increased trace and layer spacing, as well as the choice
of core and prepreg materials (such as using polyimide
versus FR4) can significantly affect the isolation withstand
of the end product.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of the LTM8047. However, these capaci
-
tors can cause problems if the LTM8047 is plugged into a
live
supply
(see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt
-
age at the V
IN
pin of the LTM8047 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8047’s rating and damaging the part. If the input
supply is poorly controlled or the user will be plugging
the LTM8047 into an energized supply, the input network
should be designed to prevent this overshoot. This can
be accomplished by installing a small resistor in series
to V
IN
, but the most popular method of controlling input
voltage overshoot is adding an electrolytic bulk capacitor
to V
IN
. This capacitor’s relatively high equivalent series
resistance damps the circuit and eliminates the voltage
overshoot. The extra capacitor improves low frequency
ripple filtering and can slightly improve the efficiency of the
circuit, though it can be a large component in the circuit.
Thermal Considerations
The LTM8047 output current may need to be derated if it
is required to operate in a high ambient temperature. The
amount of current derating is dependent upon the input
voltage, output power and ambient temperature. The
temperature rise curves given in the Typical Performance
Characteristics section can be used as a guide. These curves
were generated by the LTM8047 mounted to a 58cm
2
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
θ
JA
: Thermal resistance from junction to ambient
θ
JCbottom
: Thermal resistance from junction to the bot-
tom of the product case
θ
JCtop
: Thermal resistance from junction to top of the
product case
θ
JB
: Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased as follows:
θ
JA
is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as still air although natural convection causes the air to
move. This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
θ
JCbottom
is the junction-to-board thermal resistance with
all of the component power dissipation flowing through the
bottom of the package. In the typical µModule converter,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient envi
-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

LTM8047IY

Mfr. #:
Buy LTM8047IY
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators [Tin-Lead SnPb BGA] 725VDC Isolated DC/DC Module Converter
Lifecycle:
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