R8C/22 Group, R8C/23 Group 1. Overview
Rev.2.00 Aug 20, 2008 Page 8 of 48
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1.6 Pin Functions
Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number.
I: Input O: Output I/O: Input and output
Table 1.5 Pin Functions
Type Symbol I/O Type Description
Power Supply Input VCC
VSS
I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the
VSS pin.
Analog Power Supply
Input
AVCC, AVSS I Applies the power supply for the A/D converter. Connect
a capacitor between AVCC and AVSS.
Reset Input RESET
I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
XIN Clock Input XIN I These pins are provided for the XIN clock generation
circuit I/O. Connect a ceramic resonator or a crystal
oscillator between the XIN and XOUT pins. To use an
externally derived clock, input it to the XIN pin and leave
the XOUT pin open.
XIN Clock Output XOUT O
INT
Interrupt Input INT0 to INT3 IINT interrupt input pins.
INT0
Timer RD input pins.
INT1
Timer RA input pins.
Key Input Interrupt KI0
to KI3 I Key input interrupt input pins.
Timer RA TRAIO I/O Timer RA I/O pin.
TRAO O Timer RA output pin.
Timer RB TRBO O Timer RB output pin.
Timer RD TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O Timer RD I/O ports.
TRDCLK I External clock input pin.
Timer RE TREO O Divided clock output pin.
Serial Interface CLK0 I/O Transfer clock I/O pin.
RXD0, RXD1 I Serial data input pins.
TXD0, TXD1 O Serial data output pins.
I
2
C Bus Interface
SCL I/O Clock I/O pin.
SDA I/O Data I/O pin.
Clock Synchronous
Serial I/O with Chip
Select
SSI I/O Data I/O pin.
SCS
I/O Chip-select signal I/O pin.
SSCK I/O Clock I/O pin.
SSO I/O Data I/O pin.
CAN Module CRX0 I CAN data input pin.
CTX0 O CAN data output pin.
Reference Voltage Input VREF I Reference voltage input pin to A/D converter.
A/D Converter AN0 to AN11 I Analog input pins to A/D converter.
I/O Port P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0, P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_5,
P6_0 to P6_7
I/O CMOS I/O ports. Each port contains an input/output
select direction register, allowing each pin in that port to
be directed for input or output individually.
Any port set to input can select whether to use a pull-up
resistor or not by a program.
Input Port P4_2, P4_6, P4_7 I Input only ports.
R8C/22 Group, R8C/23 Group 1. Overview
Rev.2.00 Aug 20, 2008 Page 9 of 48
REJ03B0097-0200
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Table 1.6 Pin Name Information by Pin Number
Pin
Number
Control Pin Port
I/O Pin Functions for of Peripheral Modules
Interrupt Timer
Serial
Interface
Clock
Synchronous
Serial I/O with
Chip Select
I
2
C Bus
Interface
CAN
Module
A/D
Converter
1 P3_5 SSCK SCL
2 P3_3 SSI
3P3_4
SCS
SDA
4MODE
5P4_3
6P4_4
7
RESET
8XOUTP4_7
9 VSS/AVSS
10 XIN P4_6
11 VCC/AVCC
12 P2_7 TRDIOD1
13 P2_6 TRDIOC1
14 P2_5 TRDIOB1
15 P2_4 TRDIOA1
16 P2_3 TRDIOD0
17 P2_2 TRDIOC0
18 P2_1 TRDIOB0
19 P2_0
TRDIOA0/TRDCLK
20 P1_7
INT1
TRAIO
21 P1_6 CLK0
22 P1_5
(INT1
)
(1)
(TRAIO)
(1)
RXD0
23 P1_4 TXD0
24 P1_3
KI3
AN11
25 P4_5
INT0
INT0
26 P6_6
INT2
TXD1
27 P6_7
INT3
RXD1
28 P1_2
KI2
AN10
29 P1_1
KI1
AN9
30 P1_0
KI0
AN8
31 P3_1 TRBO
32 P3_0 TRAO
33 P6_5
34 P6_4
35 P6_3
36 P0_7 AN0
37 P0_6 AN1
38 P0_5 AN2
39 P0_4 AN3
40 VREF P4_2
41 P6_0 TREO
42 P6_2 CRX0
43 P6_1 CTX0
44 P0_3 AN4
45 P0_2 AN5
46 P0_1 AN6
47 P0_0 AN7
48 P3_7 SSO
R8C/22 Group, R8C/23 Group 2. Central Processing Unit (CPU)
Rev.2.00 Aug 20, 2008 Page 10 of 48
REJ03B0097-0200
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
comprise a register bank. Two sets of register banks are provided.
Figure 2.1 CPU Registers
R2
b31
b15 b8b7
b0
Data registers
(1)
Address registers
(1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15b19
b0
INTBL
FB
Frame base registers
(1)
The 4-high order bits of INTB are INTBH and
the 16-low order bits of INTB are INTBL.
Interrupt table register
b19
b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
C
IPL
DZSBOIU
b15
b0
b15
b0
b15
b0
b8
b7
NOTE:
1. A register bank comprises these registers. Two sets of register banks are provided.
R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)

R5F21237KFP#U1

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 48+2K -40/125C AU PbFree 48LQFP
Lifecycle:
New from this manufacturer.
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