9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 17 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2 Internal registers
The SC16C654B/654DB provides 17 internal registers for monitoring and control. These
registers are shown in Table 5. Twelve registers are similar to those already available in
the standard 16C554. These registers function as data holding registers (THR/RHR),
interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status
and control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
scratchpad register (SPR). Beyond the general 16C554 features and capabilities, the
SC16C654B/654DB offers an enhanced feature register set (EFR, Xon/Xoff1-2) that
provides on-board hardware/software flow control. Register functions are more fully
described in the following paragraphs.
[1] These registers are accessible only when LCR[7] is a logic 0.
[2] These registers are accessible only when LCR[7] is a logic 1.
[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to ‘BFh’.
6.3 FIFO operation
The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. With SC16C554 devices, the user can set the receive trigger level, but not the
transmit trigger level. The SC16C654B/654DB provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C554, the transmit interrupt
trigger level is set to 8 following a reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR register, but activation will not take place until
EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Table 5: Internal registers decoding
A2 A1 A0 Read mode Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
[1]
0 0 0 Receive Holding Register Transmit Holding Register
0 0 1 Interrupt Enable Register Interrupt Enable Register
0 1 0 Interrupt Status Register FIFO Control Register
0 1 1 Line Control Register Line Control Register
1 0 0 Modem Control Register Modem Control Register
1 0 1 Line Status Register n/a
1 1 0 Modem Status Register n/a
1 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
0 0 0 LSB of Divisor Latch LSB of Divisor Latch
0 0 1 MSB of Divisor Latch MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)
[3]
0 1 0 Enhanced Feature Register Enhanced Feature Register
1 0 0 Xon1 word Xon1 word
1 0 1 Xon2 word Xon2 word
1 1 0 Xoff1 word Xoff1 word
1 1 1 Xoff2 word Xoff2 word
