9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 39 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
10. Dynamic characteristics
Table 28: Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
=
±
10 %, unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
t
1w
, t
2w
clock pulse duration 10 - 6 - 6 - ns
f
XTAL
oscillator/clock frequency
[1] [2]
- 48 - 80 80 MHz
t
6s
address setup time 0 - 0 - 0 - ns
t
6h
address hold time 0 - 0 - 0 - ns
t
7d
IOR delay from chip select 10 - 10 - 10 - ns
t
7w
IOR strobe width 25 pF load 77 - 26 - 23 - ns
t
7h
chip select hold time from
IOR
0- 0- 0- ns
t
9d
read cycle delay 25 pF load 20 - 20 - 20 - ns
t
12d
delay from IOR to data 25 pF load - 77 - 26 - 23 ns
t
12h
data disable time 25 pF load - 15 - 15 - 15 ns
t
13d
IOW delay from chip select 10 - 10 - 10 - ns
t
13w
IOW strobe width 20 - 20 - 15 - ns
t
13h
chip select hold time from
IOW
0- 0- 0- ns
t
15d
write cycle delay 25 - 25 - 20 - ns
t
16s
data setup time 20 - 20 - 15 - ns
t
16h
data hold time 15 - 5 - 5 - ns
t
17d
delay from IOW to output 25 pF load - 100 - 33 - 29 ns
t
18d
delay to set interrupt from
Modem input
25 pF load - 100 - 24 - 23 ns
t
19d
delay to reset interrupt
from
IOR
25 pF load - 100 - 24 - 23 ns
t
20d
delay from stop to
set interrupt
-1T
RCLK
[3]
-1T
RCLK
[3]
-1T
RCLK
[3]
ns
t
21d
delay from IOR to
reset interrupt
25 pF load - 100 - 29 - 28 ns
t
22d
delay from start to set
interrupt
- 100 - 45 - 40 ns
t
23d
delay from IOW to transmit
start
8T
RCLK
[3]
24T
RCLK
[3]
8T
RCLK
[3]
24T
RCLK
[3]
8T
RCLK
[3]
24T
RCLK
[3]
ns
t
24d
delay from IOW to
reset interrupt
- 100 - 45 - 40 ns
t
25d
delay from stop to
set
RXRDY
-1T
RCLK
[3]
-1T
RCLK
[3]
-1T
RCLK
[3]
ns
t
26d
delay from IOR to
reset
RXRDY
- 100 - 45 - 40 ns
t
27d
delay from IOW to
set
TXRDY
- 100 - 45 - 40 ns