RT7021A/B
14
DS7021A/B-03 September 2016www.richtek.com
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Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Figure 5. Derating Curve of Maximum Power Dissipation
Layout Consideration
A proper PCB layout for power supply can reduce
unnecessary waveform noise and electromagnetic
interference problems to ensure proper system operation,
please refer to the following PCB layout considerations :
For the high voltage and high current loop layout of
power supply should be as thick and short. Avoid
excessive layout generated parasitic inductance and
resistors to cause significant noise.
In order to shorten the length of IC layout, you need to
consider the relative placement for IC and the power
switches. It is recommended that the power switches
placed in a symmetrical manner, and the IC close to
high-side and low-side elements.
In order to reduce the noise coupling, it is recommended
that the ground layout should not be placed under or
near the high voltage floating side.
The layout between high-side and low-side power
switches should be thick and straight, avoiding the
formation of long loops. Too long distance will increase
the loop area, and electromagnetic interference
suppression capabilities would be affected. However,
too short distance may cause overheating situation. It
is necessary to consider the most appropriate way.
Refer to typical application circuit, the VCC capacitor
(C1), BOOT to LX capacitor (C
BOOT
), and bootstrap diode
(D
BOOT
) need to be placed as close to the IC as possible
to minimize parasitic inductance and resistance. The
C
BOOT
selected range is from 0.1μF to 0.47μF, and the
VCC capacitor (C1) is greater than ten times C
BOOT
. It is
recommended to use fast or ultra fast reverse recovery
time bootstrap diode D
BOOT
.
In Figure 6, the LX pin voltage drop can be improved by
adding R
LX
(R
LX
= 1 to 10Ω), because the dv/dt is affected
by (R
LX
+ R
UGATE
).
Figure 6. LX Pin Resister
If the gate current loop opens circuit for some factors,
at this time the current flows through the gate loop via
the power MOSFET drain-to-gate parasitic capacitor. The
current will charge the gate-to-source parasitic capacitor
to result in power MOSFET wrong action. The power
switches can be damaged or burned out, the resisters
(about least 10kΩ) are connected between the gate and
source pin can prevent malfunction of the power
switches.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
DIP-8
SOP-8
LX
UGATE
R
LX
R
UGATE
BOOT
Q1
D
BOOT
+V
DC
V
CC
C
BOOT
four-layer test board. For a DIP-8 package, the thermal
resistance, θ
JA
, is 134.9°C/W on a standard JEDEC 51-7
high effective-thermal-conductivity four-layer test board.
The maximum power dissipation at T
A
= 25°C can be
calculated as below :
P
D(MAX)
= (125°C − 25°C) / (188°C/W) = 0.53W for a
SOP-8 package.
P
D(MAX)
= (125°C − 25°C) / (134.9°C/W) = 0.74W for a
DIP-8 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed T
J(MAX)
and the thermal
resistance, θ
JA
. The derating curves in Figure 5 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
