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74AC299MTCX

P1-P3P4-P6P7-P9P10-P12P13-P14
74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC299, 74ACT299 Rev. 1.4.0
January 2008
74AC299, 74ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
Features
■
I
CC
and I
OZ
reduced by 50%
■
Common parallel I/O for reduced pin count
■
Additional serial inputs and outputs for expansion
■
Four operating modes: shift left, shift right, load
and store
■
3-STATE outputs for bus-oriented applications
■
Outputs source/sink 24mA
■
ACT299 has TTL-compatible inputs
General Description
The AC/ACT299 is an 8-bit universal shift/storage regis-
ter with 3-STATE outputs. Four modes of operation are
possible: hold (store), shift left, shift right and load data.
The parallel load inputs and flip-flop outputs are multi-
plexed to reduce the total number of package pins. Addi-
tional outputs are provided for flip-flops Q
0
, Q
7
to allow
easy serial cascading. A separate active LOW Master
Reset is used to reset the register.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74AC299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC299SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC299MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT299MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC299, 74ACT299 Rev. 1.4.0 2
74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
Connection Diagram
Pin Description
Functional Description
The AC/ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift left, shift right, parallel load and hold
operations. The type of operation is determined by S
0
and S
1
, as shown in the Truth Table. All flip-flop outputs
are brought out through 3-STATE buffers to separate I/O
pins that also serve as data inputs in the parallel load
mode. Q
0
and Q
7
are also brought out on other pins for
expansion in serial shifting of longer words.
A LOW signal on MR
overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the
recommended setup and hold times, relative to the rising
edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the
3-STATE buffers and puts the I/O pins in the high imped-
ance state. In this condition the shift, hold, load and reset
operations can still occur. The 3-STATE buffers are also
disabled by HIGH signals on both S
0
and S
1
in prepara-
tion for a parallel load operation.
Logic Symbols
IEEE/IEC
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Pin Names Description
CP Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0
, S
1
Mode Select Inputs
MR
Asynchronous Master Reset
OE
1
, OE
2
3-STATE Output Enable Inputs
I/O
0
–I/O
7
Parallel Data Inputs or 3-STATE
Parallel Outputs
Q
0
, Q
7
Serial Outputs
Inputs Response
MR S
1
S
0
CP
LXXXAsynchronous Reset;
Q
0
–Q
7
=
LOW
HHH Parallel Load; I/O
n
→
Q
n
HLH Shift Right;
DS
0
→
Q
0
, Q
0
→
Q
1
, etc.
HHL Shift Left,
DS
7
→
Q
7
, Q
7
→
Q
6
, etc.
HLLXHold
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC299, 74ACT299 Rev. 1.4.0 3
74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
P1-P3P4-P6P7-P9P10-P12P13-P14

74AC299MTCX

Mfr. #:
Buy 74AC299MTCX
Manufacturer:
ON Semiconductor
Description:
IC SHIFT/REGISTER STORE 20TSSOP
Lifecycle:
New from this manufacturer.
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