TEA18361LT/1J Datasheet TEA18361LT/1J | P13-P15

Product data sheet Rev. 2 — 12 December 2013 13 of 29

NXP Semiconductors

TEA18361LT

GreenChip SMPS control IC

Using a 10 F VCC capacitor, the fast latch reset time is below 0.6 s. If the mains is not

shorted but removed, a discharged of the X-cap can cause an additional waiting time.

7.7 Burst mode operation (CTRL pin)

The controller enters the burst mode when a low output power causes the voltage on the

CTRL pin to drop below 0.5 V.

During normal operation, the primary opto current can be calculated with Equation 1

(1)

This implies that without any additional measure, the maximum primary opto current in

burst mode is:

(2)

Depending on the optocoupler used , the secondary opto current is even higher.

To achieve minimum no load input power, the internal voltage (7 V) is regulated to a value

that causes the primary opto current value to be 100 A when the system is in burst

mode. The secondary opto current is then automatically also within this lower range. If the

IC detects that the opto current is lower than 80 A, the internal voltage is increased faster

to achieve a small output voltage undershoot at a positive load step. Once the system

enters normal operation mode, the internal voltage is slowly increased to 7 V again.

Fig 10. Fast latch reset

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Product data sheet Rev. 2 — 12 December 2013 14 of 29

NXP Semiconductors

TEA18361LT

GreenChip SMPS control IC

To avoid audible noise, a special digital burst mode is implemented. The minimum

switching frequency in this mode is 25 kHz. The burst mode repetition rate has a target

frequency of 800 Hz (1250 s; see Figure 11

The amount of pulses at each burst period is defined by the requested output power. At

higher output power, the amount of switching pulses increases. At low load, it decreases.

The digital circuit defines the amount of burst cycles so that the burst frequency is below

the audible range (800 Hz) and the switching frequency exceeds the audible range

(25 kHz). Any audible noise is avoided.

The minimum amount of switching cycles is set to 3 to ensure good efficiency at very low

loads. To regulate the output power at a very low load, the system increases the burst

period (< 800 Hz). The increased burst period is still outside the audible range.

To further improve the no load input power and efficiency at low loads, the current

consumption of the IC is lowered to 235 A during the non-switching period in the burst

mode.

To achieve a good transient response in burst mode, the system starts switching

immediately at an increased output load, allowing a shorter burst period. Eventually, it

regulates to the required burst period by increasing the amount of driver pulses

(see Figure 12

Fig 11. Burst mode operation

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Product data sheet Rev. 2 — 12 December 2013 15 of 29

NXP Semiconductors

TEA18361LT

GreenChip SMPS control IC

Due to the discrete number of switching cycles, the new calculated number of pulses must

be 0.5 higher or lower than the existing number before one switching cycle is added or

taken away. For the IC to increase or decrease the amount of switching cycles, a certain

deviation from the target burst repetition frequency (800 Hz) is required because of the

internal algorithm. This deviation becomes smaller when the amount of switching cycles

increases. Figure 13

shows the upper and lower limits of the burst repetition frequency as

a function of the number of pulses.

When the amount of driver pulses within one burst period exceeds 40, the system

switches to normal mode again.

During the burst period, the voltage on the CTRL pin is clamped to the minimum

clamp(CTRL)

. The current out of the CTRL pin is measured. If the current exceeds

stop(CTRL)

, the burst period is terminated regardless of digital control. This feature ensures

a small overshoot at the output voltage when the load in burst mode suddenly reduces.

At the end of each burst period, the CTRL pin is pulled to the ground level for 12.5 s,

unless the current flowing from pin CTRL < 87 A, which usually occurs at a positive load

step.

Fig 12. Transient response in burst mode

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P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

TEA18361LT/1J

Mfr. #:

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Manufacturer:

NXP Semiconductors

Description:

Switching Controllers GreenChip SMPS contr control IC

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