LTC3113
7
3113f
PIN FUNCTIONS
V
OUT
(Pins 1, 2/Pins 2, 3): Buck-Boost Output Voltage. A
low ESR capacitor should be placed from V
OUT
to PGND.
The capacitor should be placed as close to the IC as pos-
sible and have a short return path to ground.
V
IN
(Pins 3, 4, 5/Pins 4, 5, 6): Power Input for the
Converter. A 47μF or larger bypass capacitor should be
connected between V
IN
and PGND. The bypass capacitor
should located as close to V
IN
and PGND as possible and
should via directly to the ground plane.
SGND (Pin 6/Pin 7): Signal Ground. Terminate the fre-
quency setting resistor and output voltage divider to SGND.
BURST (Pin 7/Pin 8): Pulse Width Modulation/Burst Mode
Selection Input. Forcing this pin low causes the switching
converter to operate in low noise fi xed frequency PWM
mode. Forcing this pin high enables constant Burst Mode
operation for the converter. During Burst Mode operation,
the converter can only support a reduced maximum load
current.
RT (Pin 8/Pin 9): Programs the Frequency of the Internal
Oscillator. Connect a resistor from RT to ground (SGND).
The R
T
resistor value for a given frequency is given by the
following equation.
R
T
90
fMHz
()
kΩ
()
VC (Pin 9/Pin 12): Error Amp Output. An R-C network is
connected from this pin to FB for loop compensation. Refer
to the Closing the Feedback Loop section for component
selection guidelines.
FB (Pin 10/Pin 13): Feedback Voltage for the Buck-Boost
Converter Derived from a Resistor Divider on the Buck-
Boost Output Voltage. The buck-boost output voltage is
given by the following equation:
V
OUT
= 0.600 1+
R2
R1
V
()
where R1 is a resistor connected between FB and SGND,
and R2 is a resistor connected between FB and V
OUT
. The
buck-boost output voltage can be adjusted from 1.8V to
5.5V.
RUN (Pin 11/Pin 14): Active High Converter Enable In-
put. Applying a voltage <0.3V to this pin shuts down the
LTC3113. Applying a voltage >1.2V to this pin enables
the LTC3113.
SW1 (Pins 12, 13, 14/Pins 15, 16, 17): Switch Pin Where
Internal Switches A and B are Connected. Connect the
inductor from SW1 to SW2. Minimize trace length to
reduce EMI.
SW2 (Pins 15, 16/Pins 18, 19): Switch Pin Where Internal
Switches C and D are Connected. Connect the inductor
from SW1 to SW2. Minimize trace length to reduce EMI.
PGND (Exposed Pad Pin 17/Pins 1, 10, 11, 20, Exposed
Pad Pin 21): The exposed pad must be soldered to the
PCB and electrically connected to ground through the
shortest and lowest impedance connection possible.
In most applications the bulk of the heat fl ow out of the
LTC3113 is through this pad, so printed circuit board
design has an impact on the thermal performance of the
part. See the PCB Layout and Thermal Considerations
section for more details.
(DFN/TSSOP)
LTC3113
8
3113f
DETAILED BLOCK DIAGRAM
+
1.6V
SLEEP
UVLO
+
+
+
+
+
11.1A
V
IN
SWA
V
IN
1.8V TO 5.5V
SWD
SWC
REVERSE
CURRENT
LIMIT
SWB
SW1
SW2
2.2μH
PEAK
CURRENT
LIMIT
PWM
COMPARATORS
ERROR
AMP
7.8A
–1.0A
INPUT
CURRENT
LIMIT
SOFT-START
0.6V
FB
V
OUT
VC
R
Z
49.9k
C
P1
680pF
C
P2
12pF
1 = ON
0 = OFF
PWM
LOGIC
AND
OUTPUT
PHASING
Burst Mode
CONTROL
RUN LOGIC
GATE
DRIVERS
AND
ANTICROSS
CONDUCTION
OSC
RUN
RUN
SGND
RT
R
T
90.9k
1 = BURST
0 = PWM
BURST
+
+
R1
158k
3113 BD
R2
845k
R
Z2
6.49k
C
Z1
47pF
C
L
100μF
+
10
9
11
6
PGND
17
7
8
3
1312 14 15 16
1
2
4
5
(DFN Package)
LTC3113
9
3113f
OPERATION
INTRODUCTION
The LTC3113 is a low noise, high power synchronous
buck-boost DC/DC converter optimized for demanding
applications. The LTC3113 utilizes a proprietary switching
algorithm, which allows its output voltage to be regulated
above, below or equal to the input voltage. The error ampli-
er output (VC) determines the output duty cycle of each
switch. The low R
DS(ON)
, low gate charge, synchronous
power switches provide high frequency pulse width modu-
lation control. High effi ciency is achieved at light loads
when Burst Mode operation is commanded.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator
The frequency of operation can be programmed between
300kHz and 2MHz by an external resistor from the RT pin
to ground, according to the following equation:
R
T
90
fMHz
()
kΩ
()
Error Amplifi er
The error amplifi er is a high gain voltage mode ampli-
er. The loop compensation components are confi gured
around the amplifi er (from FB to VC) to obtain stable
converter operation. For improved bandwidth, an addi-
tional RC feedforward network can be placed across the
upper feedback divider resistor. Refer to the Applications
Information section of this data sheet under Closing the
Feedback Loop for information on selecting compensation
type and components.
Current Limit Operation
The buck-boost converter has two current limit circuits.
The primary current limit is an average current limit cir-
cuit which sources current into FB to reduce the output
voltage, should the input current exceed 7.8A. Due to the
high gain of the feedback loop, the injected current forces
the error amplifi er output to decrease until the average
current through switch A decreases approximately to the
current limit value. The average current limit utilizes the
error amplifi er in an active state and thereby provides a
smooth recovery with little overshoot once the current
limit fault condition is removed. Since the current limit is
based on the average current through switch A, the peak
inductor current in current limit will have a dependency
on the duty cycle (i.e., on the input and output voltages)
in the overcurrent condition. For this current limit feature
to be most effective, the Thevenin resistance from FB to
ground should exceed 100k.
The speed of the average current limit circuit is limited
by the dynamics of the error amplifi er. On a hard output
short, it is possible for the inductor current to increase
substantially beyond current limit before the average cur-
rent limit circuit would react. For this reason, there is a
second current limit circuit which turns off switch A if the
current ever exceeds approximately 142% of the average
current limit value. This provides additional protection in
the case of an instantaneous hard output short.
Should the output voltage become less then 1.2V nomi-
nally, both the current limits are reduced compared to the
normal operating current limits.
Reverse Current Limit
During fi xed frequency operation, a reverse-current com-
parator on switch D monitors the current entering V
OUT
.
When this current exceeds 1A (typical) switch D will be
turned off for the remainder of the switching cycle. This
feature protects the buck-boost converter from excessive
reverse current if the buck-boost output is held above the
regulation voltage by an external source.
In applications where the oscillator frequency is pro-
grammed above 1MHz and the output voltage is held above
its programmed regulation value, reverse currents greater
than 1A (typical) may be observed. In conjunction with
oscillator frequencies higher than 1MHz, higher output
voltages will also increase the magnitude of observed
reverse current. Refer to the Negative Inductor Current
vs Oscillator Frequency graph in the Typical Performance
Characteristics section for typical variations.

LTC3113IDHD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3A Wide Vin, Low Noise Buck-Boost DC/DC Converter
Lifecycle:
New from this manufacturer.
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