CBTD3384 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 12 December 2012 6 of 17
NXP Semiconductors
CBTD3384
10-bit level shifting bus switch with 5-bit output enables
(1) I
SW
= 100 A
(2) I
SW
= 6 mA
(3) I
SW
=12 mA
(4) I
SW
= 24 mA
(1) I
SW
= 100 A
(2) I
SW
= 6 mA
(3) I
SW
=12 mA
(4) I
SW
= 24 mA
Fig 7. Pass voltage versus supply voltage;
T
amb
=25C (typical)
Fig 8. Pass voltage versus supply voltage;
T
amb
=0C (typical)
001aak836
V
CC
(V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
V
pass
(V)
2.0
(4)
(1)
(2)
(3)
001aak837
V
CC
(V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
V
pass
(V)
2.0
(4)
(1)
(3)
(2)
(1) I
SW
= 100 A
(2) I
SW
= 6 mA
(3) I
SW
=12 mA
(4) I
SW
= 24 mA
Fig 9. Pass voltage versus supply voltage; T
amb
= 40 C (typical)
001aak838
V
CC
(V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
V
pass
(V)
2.0
(1)
(3)
(2)
(4)
CBTD3384 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 12 December 2012 7 of 17
NXP Semiconductors
CBTD3384
10-bit level shifting bus switch with 5-bit output enables
10. Dynamic characteristics
[1] The propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
[2] t
pd
is the same as t
PLH
and t
PHL
.
t
en
is the same as t
PZL
and t
PZH
.
t
dis
is the same as t
PLZ
and t
PHZ
.
11. Waveforms
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.
Symbol Parameter Conditions T
amb
= 40 C to +85 C Unit
Min Typ Max
t
pd
propagation delay nAn, nBn to nBn, nAn; see Figure 10
[1][2]
V
CC
= 5.0 V 0.5 V - - 0.25 ns
t
en
enable time nOE to nAn or nBn; see Figure 11
[2]
V
CC
= 5.0 V 0.5 V 1.2 4.3 7.0 ns
t
dis
disable time nOE to nAn or nBn; see Figure 11
[2]
V
CC
= 5.0 V 0.5 V 1.7 3.0 5.3 ns
Measurement points are given in Table 8.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 10. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times
001aan063
nAn, nBn,
input
nBn, nAn,
output
GND
V
I
V
OH
V
OL
V
M
t
PHL
t
PLH
V
M
CBTD3384 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 12 December 2012 8 of 17
NXP Semiconductors
CBTD3384
10-bit level shifting bus switch with 5-bit output enables
Measurement points are given in Table 8.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 11. Enable and disable times
001aak298
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
nOE input
V
I
3.5 V
V
M
V
M
V
OL
V
OH
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
V
X
V
Y
V
CC
= 5.0 V 0.5 V GND to 3.0 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V

CBTD3384DB,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Digital Bus Switch ICs 10BIT LVL SHIFT BUS
Lifecycle:
New from this manufacturer.
Delivery:
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