Third Stage (Power Stage)
This last stage delivers 30dBm to a 50Ω load. It oper-
ates in Class E to achieve a high power-added efficien-
cy (PAE). Proper output matching is required for
optimal output power. The output of the power stage
requires a low-series-resistance pull-up inductor with a
minimum current rating of 1.5A. See the Typical
Operating Circuit for an example of an output matching
circuit.
Biasing and Power Control
SHDN, GC, RAMP, and REF are bias and power-control
pins. Drive SHDN below 0.5V to turn off the entire chip,
and drive SHDN above 2.0V to turn on the device.
When SHDN is high, a V
GC
from 0.6V to 2.3V continu-
ously controls the gain in the first stage (VGA) and the
output power.
Drive GC below 0.4V to put the device in standby mode
with only the first stage on. If GC is unconnected and
V
SHDN
> 2.0V, the device is set to maximum gain.
Table 1 summarizes these operating modes.
Power Ramping Control
A capacitor connected between RAMP and REF con-
trols the output power rise/fall time to reduce transient
noise when SHDN turns the device on and off. Because
the ramp is approximately a raised cosine, this device
can be used in direct On/Off Keying (OOK) applications
with minimum intersymbol interference. The value of the
ramping capacitor is determined from the Rise/Fall Time
vs. Ramping Capacitance curves in the Typical
Operating Characteristics.
Table 1. Operating Modes
Board Assembly Precaution
Solder the underside metal slug evenly to the board
ground plane for optimal performance. Fill all vias in the
area under the slug. For maximum power gain and sat-
urated output power, ensure that the entire slug makes
contact with the board ground.
MAX2235
+3.6V, 1W Autoramping Power
Amplifier for 900MHz Applications
_______________________________________________________________________________________ 7
GC
SHDN
>2.0V >0.6V
MODE
On
Standby>2.0V <0.4V
Shutdown<0.5V Don’t care
Chip Information
TRANSISTOR COUNT: 668
